Contacts for fet devices

Abstract

A device characterized as being an FET device structure with enlarged contact areas is disclosed. The device has a vertically recessed isolation, thereby having an exposed sidewall surface on both the source and the drain. A silicide layer is covering both the top surface and the sidewall surface of both the source and the drain. Metallic contacts to the device engage the silicide layer on its top surface and on its sidewall surface.

1 . A device, comprising:
 a body having an upper surface, a gate-stack, a source and a drain, wherein said body upper surface defines a principal surface for said device;   an isolation surrounding said device, wherein at least a portion of said isolation is recessed in a vertically offset position relative to said principal surface, wherein due to said portion of said insulation that is recessed a sidewall surface on both said source and said drain are exposed;   a silicide layer covering top surfaces on both said source and said drain and said sidewall surface of both said source and said drain, wherein said top surfaces are substantially parallel with said principal surface;   metallic contacts to said source and said drain, wherein said metallic contacts engage said silicide layer on said top surfaces and on said sidewall surface of at least one of said source and of said drain; and   wherein said gate-stack overlays a part of said isolation, wherein said part of said isolation underneath said gate-stack is essentially even with said principal surface, and wherein said device is characterized as being an FET device structure with contacts.   
     
     
         2 . The device of  claim 1 , wherein said metallic contacts engage said silicide layer on said sidewall surface of both of said source and of said drain. 
     
     
         3 . The device of  claim 1 , wherein said FET device structure is a semiconductor on insulator (SOI) FET device structure. 
     
     
         4 . The device of  claim 3 , wherein said portion said isolation that is recessed is fully removed down to an insulator, wherein said insulator is a buried insulator of a SOI substrate for said SOI FET device structure. 
     
     
         5 . The device of  claim 4 , wherein said isolation is a shallow trench isolation (STI). 
     
     
         6 . The device of  claim 5 , wherein said sidewall surface is substantially perpendicular to said principal surface. 
     
     
         7 . The device of  claim 5 , wherein said STI is of essentially silicon oxide. 
     
     
         8 . The device of  claim 1 , wherein said metallic contacts are of an elongated form and said source and said drain both have a width, and wherein said elongated form is positioned along at least a portion of said width of said source and said drain. 
     
     
         9 . The device of  claim 1 , wherein said source and said drain both have corners, and said metallic contacts engage said silicide layer at said corners of said source and said drain. 
     
     
         10 . A device, comprising:
 a body having an upper surface, a source and a drain, wherein said body upper surface defines a principal surface for said device;   an isolation surrounding said device, wherein at least a portion of said isolation is recessed in a vertically offset position relative to said principal surface, wherein due to said portion of said insulation that is recessed a sidewall surface on both said source and said drain are exposed;   a silicide layer covering top surfaces on both said source and said drain and said sidewall surface of both said source and said drain, wherein said top surfaces are substantially parallel with said principal surface;   metallic contacts to said source and said drain, wherein said metallic contacts engage said silicide layer on said top surfaces and on said sidewall surface of at least one of said source and of said drain; and   wherein said device is characterized as being a semiconductor on insulator (SOI) FET device structure with contacts, and wherein said portion said isolation that is recessed is fully removed down to an insulator, wherein said insulator is a buried insulator of a SOI substrate for said SOI FET device structure.   
     
     
         11 . The device of  claim 10 , wherein said metallic contacts engage said silicide layer on said sidewall surface of both of said source and of said drain. 
     
     
         12 . The device of  claim 10 , wherein said SOI FET device structure further comprises a gate-stack, wherein said gate-stack overlays a part of said isolation, wherein said part of said isolation underneath said gate-stack is essentially even with said principal surface. 
     
     
         13 . The device of  claim 10 , wherein said isolation is a shallow trench isolation (STI). 
     
     
         14 . The device of  claim 13 , wherein said sidewall surface is substantially perpendicular to said principal surface. 
     
     
         15 . The device of  claim 13 , wherein said STI is of essentially silicon oxide. 
     
     
         16 . The device of  claim 10 , wherein said metallic contacts are of an elongated form and said source and said drain both have a width, and wherein said elongated form is positioned along at least a portion of said width of said source and said drain. 
     
     
         17 . The device of  claim 10 , wherein said source and said drain both have corners, and said metallic contacts engage said silicide layer at said corners of said source and said drain.