Dma transfer control device

Abstract

A DMA transfer control device comprises: a DMA arbiter performing DMA transfer for each DMA channel formed by a combination of a memory and a plurality of input/output devices and DMA controller circuits controlling the DMA arbiter; a judgment unit and a transfer time calculation unit calculating a next DMA transfer scheduled time based on the DMA transfer size for a DMA transfer request and a judgment time. A timer counter timing the judgment time at a unit time interval, and a comparator comparing the judgment time where a DMA transfer request arrives with the DMA transfer scheduled time are also provided, and the judgment unit sends the DMA transfer permission to the DMA arbiter upon an output of the comparator indicating the judgment time is not earlier than the DMA transfer scheduled time. Data is efficiently transferred by dynamically controlling DMA transfer.

1 . A Direct Memory Access (DMA) transfer control device, comprising:
 a DMA arbiter that performs DMA transfer for each DMA channel formed by a combination of a memory and a plurality of input/output devices; and   a DMA controller circuit that controls the DMA arbiter;   a judgment unit that sends a DMA transfer permission to said DMA arbiter in a case where a judgment time at which a DMA transfer request arrives from said input/output device is not earlier than a DMA transfer scheduled time and rejects another DMA transfer request from said input/output device when the another DMA transfer request arrives earlier than the DMA transfer scheduled time; and   a transfer time calculation unit that calculates a next round of said DMA transfer scheduled time based on a DMA transfer size for said DMA transfer request and said judgment time.   
     
     
         2 . The DMA transfer control device as defined in  claim 1 , further comprising:
 a timer counter that times said judgment time at a unit time interval; and   a comparator that compares said judgment time at which said DMA transfer request arrives with said DMA transfer scheduled time; wherein   said judgment unit sends the DMA transfer permission to said DMA arbiter when an output of said comparator indicates that said judgment time is not earlier than said DMA transfer scheduled time and does not send the DMA transfer permission to said DMA arbiter when the output of said comparator indicates that said judgment time is earlier than said DMA transfer scheduled time.   
     
     
         3 . The DMA transfer control device as defined in  claim 1 , wherein said transfer time calculation unit comprises a calculation unit that multiplies a set value of a DMA transfer size for said DMA transfer request by a set value of a DMA transfer interval for unit DMA transfer size to create a multiplication result, and that adds said judgment time to the multiplication result; and 
       a register that holds the calculation result of said calculation unit as a next round of said DMA transfer scheduled time.: