Semiconductor device having controllable transistor threshold voltage

Abstract

In an embodiment, a semiconductor device includes a single-layer gate nonvolatile memory in which a floating gate is formed on a semiconductor substrate. The floating gate is formed above a diffusion layer serving as a control gate of the nonvolatile memory. The diffusion layer may be insulated from the semiconductor substrate by an insulating film such as a silicon oxide film. A pair of diffusion layers may be formed in surface regions of the semiconductor substrate on the two sides of the floating gate extending on a tunnel oxide film in an embodiment. The configuration described herein may realize a reliable semiconductor device in a low-cost process, may have a control gate which may withstand a high voltage applied when data is erased or written, and may prevent an operation error by minimizing variations in the threshold value, in some embodiments.

1 . A method comprising:
 forming a transistor in a first element active region of a semiconductor substrate, wherein the transistor has a gate electrode;   forming a first conductive region in a second element active region of the semiconductor substrate, wherein the first element active region is electrically isolated from the second element active region, and wherein the first conductive region is a control gate of a non-volatile memory;   forming an additional electrode over at least a portion of the first conductive region, wherein the additional electrode is separated from the first conductive region by a dielectric; and   electrically connecting the additional electrode to the gate electrode to form a floating gate of the non-volatile memory, wherein at least a portion of the floating gate includes a metal.   
     
     
         2 . The method of  claim 1 , wherein the metal comprises a metal film, and wherein said electrically connecting the additional electrode to the gate electrode comprises forming the metal film. 
     
     
         3 . The method of  claim 1 , further comprising:
 forming a logic gate, wherein said forming the logic gate is performed in parallel with said forming a transistor, said forming a first conductive region, said forming an additional electrode, and said electrically connecting the additional electrode to the gate electrode, and wherein said forming a logic gate further includes forming an interconnect between transistors of the logic gate, and wherein said forming an interconnect is performed in parallel with said electrically connecting the additional electrode to the gate electrode.   
     
     
         4 . The method of  claim 1 , wherein the gate electrode of the transistor is poly-silicon. 
     
     
         5 . The method of  claim 1 , wherein an entirety of the floating gate electrode is the metal. 
     
     
         6 . The method of  claim 5 , wherein the gate electrode of the transistor is poly-silicon. 
     
     
         7 . The method of  claim 1 , wherein the metal comprises aluminum. 
     
     
         8 . The method of  claim 1 , wherein the metal comprises platinum. 
     
     
         9 . The method of  claim 1 , wherein the metal comprises titanium. 
     
     
         10 . The method of  claim 1 , wherein the metal comprises ruthenium. 
     
     
         11 . The method of  claim 1 , wherein the metal comprises tungsten. 
     
     
         12 . A method comprising:
 forming a logic gate; and   forming a non-volatile memory, said forming including:
 forming a transistor in a first element active region of a semiconductor substrate; 
 forming a first conductive region in a second element active region of the semiconductor substrate that is electrically isolated from the first element active region; 
 forming a dielectric over the first conductive region; and 
 forming a floating gate electrode between a gate of the transistor and an area over the dielectric, wherein at least a portion of the floating gate electrode includes a metal. 
   
     
     
         13 . The method of  claim 12 , wherein the gate of the transistor comprises a gate electrode. 
     
     
         14 . The method of  claim 13 , wherein an entirety of the floating gate electrode between the gate electrode and the area over the dielectric is the metal. 
     
     
         15 . The method of  claim 14 , wherein the gate electrode of the transistor is poly-silicon. 
     
     
         16 . The method of  claim 12 , wherein the metal comprises aluminum. 
     
     
         17 . The method of  claim 12 , wherein the metal comprises platinum. 
     
     
         18 . The method of  claim 12 , wherein the metal comprises titanium. 
     
     
         19 . The method of  claim 12 , wherein the metal comprises ruthenium. 
     
     
         20 . The method of  claim 12 , wherein the metal comprises tungsten.