Low Power Memory Device

Abstract

“A method of operation within a memory device comprises receiving address information and corresponding enable information. The address information includes a row address that specifies a row of storage cells within a storage array of the memory device, and the enable information includes first and second enable values that correspond respectively to first and second storage locations within the row of storage cells. The method involves selectively transferring data between the first storage location and the sense amplifier circuitry if the first enable value is in an enable state and transferring data between the second storage location and the sense amplifier circuitry if the second enable value is in the enable state. The states of the first and second enable values may be separately controlled.”

1 . (canceled) 
     
     
         2 . A memory device comprising a request interface, a bank of memory, and circuitry operable to service memory commands received at the request interface, the memory device further comprising a register operable to store information and circuitry operable to perform refresh for a variable portion of the bank of memory according to the state of the information stored in the register. 
     
     
         3 . The memory device of  claim 2 , where the request interface is operable to receive a refresh command and where the memory device is operable to limit application of the refresh command received at the request interface according to the state of the information. 
     
     
         4 . The memory device of  claim 2 , where the request interface is operable to receive a self-refresh command and where the memory device is operable to limit application of the received self-refresh command to the variable portion according to the state of the information. 
     
     
         5 . The memory device of  claim 2 , where the request interface is operable to receive an auto-refresh command and where the memory device is operable to limit application of the received auto-refresh command to the variable portion according to the state of the information. 
     
     
         6 . The memory device of  claim 2 , where the circuitry operable to perform the refresh is operable to activate rows of memory associated with the variable portion and is operable to withhold activation of rows of memory not associated with the variable portion. 
     
     
         7 . The memory device of  claim 2 , where the circuitry operable to perform the refresh is operable to cause the memory device to sense rows of memory associated with the variable portion and is operable to cause the memory device to withhold sensing of rows of memory not associated with the variable portion. 
     
     
         8 . The memory device of  claim 2 , where the circuitry operable to perform the refresh is operable to cause the memory device to precharge one or more sense amplifier groups associated with the specific portion and is operable to withhold precharge of one or more sense amplifier groups not associated with the specific portion. 
     
     
         9 . The memory device of  claim 2 , where the memory device further comprises bank portions, where the information further comprises a bit of information for each respective bank portion, and where the memory device is operable to perform the refresh for each respective bank portion according to state of the respective bit. 
     
     
         10 . A memory device comprising a request interface, a bank of memory, and circuitry operable to service memory commands received at the request interface, the memory device further comprising a register operable to store information and circuitry operable to perform refresh of rows of memory cells within the bank of memory in response to a refresh command, where the memory device is operable to limit application of the refresh command to a variable portion of the bank of memory responsive to the state of the information stored in the register. 
     
     
         11 . The memory device of  claim 10 , where the request interface is operable to receive the refresh command and where the memory device is operable to limit application of the refresh command received at the request interface according to the state of the information. 
     
     
         12 . The memory device of  claim 11 , where the refresh command includes a self-refresh command. 
     
     
         13 . The memory device of  claim 11 , where the refresh command includes an auto refresh command. 
     
     
         14 . The memory device of  claim 10 , where the circuitry operable to perform refresh of the rows of memory cells is operable to activate rows of memory associated with the variable portion and is operable to withhold activation of rows of memory not associated with the variable portion. 
     
     
         15 . The memory device of  claim 10 , where the circuitry operable to perform refresh of the rows of memory cells is operable to sense of rows of memory associated with the variable portion and is operable to withhold sensing of rows of memory not associated with the variable portion. 
     
     
         16 . The memory device of  claim 10 , where the circuitry operable to perform refresh of the rows of memory cells is operable to precharge a sense amplifier group associated with the specific portion and is operable to withhold precharge of a sense amplifier group not associated with the specific portion. 
     
     
         17 . The memory device of  claim 16 , where the memory device further comprises subbanks, each sense amplifier group associated with a respective subbank, and where the information further comprises a bit of information for each respective subbank. 
     
     
         18 . A memory device comprising a request interface, a bank of memory, circuitry operable to service memory commands received at the request interface, a register operable to store information and circuitry operable to perform refresh of rows of memory cells within the bank of memory in response to a refresh command received at the request interface, where the memory device further comprises a first mode and a second mode, the memory device operable to exhibit a reduced power state in the second mode relative to the first mode, the memory device being operable in the second mode to limit application of the received refresh command to a specific portion of the bank of memory responsive to the state of the information stored in the register irrespective of any information in the bank of memory outside of the specific portion, the memory device not operable in the first mode to limit application of the received refresh command to the specific portion of the bank of memory. 
     
     
         19 . The memory device of  claim 18 , where the circuitry operable to perform refresh of the rows of memory cells is operable to activate rows of memory associated with the specific portion and is operable to withhold activation of rows of memory not associated with the specific portion. 
     
     
         20 . The memory device of  claim 18 , where the bank of memory comprises bank portions and where the information comprises a multibit word, each bit corresponding to one of the bank portions, each bit according to its state operable to indicate whether the corresponding bank portion is to receive application of the received refresh command or is to have application of the received refresh command withheld. 
     
     
         21 . The memory device of  claim 18 , where the request interface is operable to receive at least one of a self-refresh command or an auto-refresh command and where the memory device is operable to limit application of the received at least one command to the specific portion according to the state of the information. 
     
     
         22 . The memory device of  claim 18 , where the memory device is operable to receive the information in association with each memory command received at the request interface. 
     
     
         23 . The memory device of  claim 18 , where the register is an enable register, where the memory device further comprises a configuration register operable to store an indicator identifying the first mode or the second mode, where the memory device is operable to apply one of the first mode or second mode in dependence on content of the configuration register, and where the indicator stored by the configuration register is independent from the information stored by the enable register. 
     
     
         24 . The memory device of  claim 23 , further comprising an enable interface, where the memory device is to receive the information via the enable interface. 
     
     
         25 . The memory device of  claim 23 , where the memory device is operable to dynamically change content of the configuration register in response to programming commands received at the request interface. 
     
     
         26 . The memory device of  claim 18 , embodied as a dynamic random access memory (DRAM) memory device. 
     
     
         27 . A memory apparatus comprising memory devices, each memory device having a request interface coupled in common to a shared request path, a bank of memory, and circuitry operable to service memory commands received at the request interface, each memory device further comprising a register operable to store information and circuitry operable to perform refresh of rows of memory cells within the respective bank of memory in response to a refresh command received at the respective request interface, where each memory device is operable to limit application of the received refresh command to a variable portion of the respective bank of memory responsive to the state of the information stored in the respective register. 
     
     
         28 . The memory apparatus of  claim 27 , where the register of each memory device coupled in common to the shared request path is programmed to store common information, such that the variable portion of the bank of memory is programmed to be the same for each of the memory devices. 
     
     
         29 . The memory apparatus of  claim 27 , embodied as a multi-chip module. 
     
     
         30 . The memory apparatus of  claim 27 , where each memory device is embodied as a dynamic random access memory (DRAM) memory device. 
     
     
         31 . The memory apparatus of  claim 27 , where:
 the bank of each memory device further comprises bank portions;   the register of each memory device stores a multibit word of the information, each bit of the multibit word corresponding to a respective one of the bank portions; and   each memory device is operable to refresh rows of memory in each one of its bank portions according to the state of the corresponding bit of the multibit word of the information.   
     
     
         32 . The memory apparatus of  claim 31 , where each bit is an enable bit and where each memory device is further operable to perform memory transactions by activating only a select portion of at least one of a row or a column transfer for each memory transaction, where each of one or more subbanks corresponding to the select bank portion has a corresponding respective enable bit matching a first state, and where each of one or more subbanks not corresponding to the select bank portion has a corresponding respective enable bit matching a second state. 
     
     
         33 . The memory apparatus of  claim 31 , where each memory device comprises four banks of memory, each bank of memory comprises four of the bank portions, and the circuitry operable to service memory commands received at the request interface is further operable to receive a bank address in association with each of the memory commands. 
     
     
         34 . The memory apparatus of  claim 33 , where each bank portion comprises a respective subbank. 
     
     
         35 . A memory device comprising a request interface, a bank of memory, and circuitry operable to service memory commands received at the request interface, the memory further comprising means for selectively limiting application of a refresh operation to a variable portion of the bank of memory.