US2012280403A1PendingUtilityA1

Semiconductor Die and Method of Forming through Organic Vias having Varying Width in Peripheral Region of the Die

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Individually held — no corporate assignee on recordPriority: Mar 17, 2009Filed: Jul 19, 2012Published: Nov 8, 2012
Est. expiryMar 17, 2029(~2.6 yrs left)· nominal 20-yr term from priority
Inventors:Reza A. PagailaByung Tai DoShuangwu Huang
H10P 72/74H10W 90/722H10W 74/142H10W 74/00H10W 72/9415H10W 72/9413H10W 72/07251H10W 72/952H10W 72/942H10W 72/923H10W 72/922H10W 72/884H10W 72/90H10W 72/20H10W 70/655H10W 70/635H10W 70/093H10W 70/60H10W 90/00H10W 74/111H10W 74/019H10W 72/0198H10W 70/614H10W 72/9445H10W 72/072H10W 70/09H10W 72/019H10W 70/095
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Claims

Abstract

A plurality of semiconductor die is mounted to a carrier separated by a peripheral region. An insulating material is deposited in the peripheral region. A first opening is formed in the insulating material of the peripheral region to a first depth. A second opening is formed in the insulating material of the peripheral region centered over the first opening to a second depth less than the first depth. The first and second openings constitute a composite through organic via (TOV) having a first width in a vertical region of the first opening and a second width in a vertical region of the second opening. The second width is different than the first width. A conductive material is deposited in the composite TOV to form a conductive TOV. An organic solderability preservative (OSP) coating is formed over a contact surface of the conductive TOV.

Claims

exact text as granted — not AI-modified
1 . A semiconductor device, comprising:
 a semiconductor die;   an insulating material deposited in a peripheral region around the semiconductor die;   a plurality of conductive vias formed partially through the insulating material, the conductive vias including a first width in a first vertical region of the insulating material and a second width different from the first width in a second vertical region of the insulating material; and   a first conductive layer formed between a first one of the conductive vias and a contact pad of the semiconductor die.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the conductive vias extend from the insulating material. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the conductive vias are recessed in the peripheral region. 
     
     
         4 . The semiconductor device of  claim 1 , further including an organic solderability preservative (OSP) coating formed over a surface of the conductive vias. 
     
     
         5 . The semiconductor device of  claim 1 , further including a plurality of rows of the conductive vias formed in the insulating material. 
     
     
         6 . The semiconductor device of  claim 1 , further including a plurality of stacked semiconductor die electrically connected through the conductive vias. 
     
     
         7 . A semiconductor device, comprising:
 a semiconductor die;   a first insulating material deposited in a peripheral region around the semiconductor die;   a first conductive via formed in the first insulating material, the first conductive via including a first width and a second width different from the first width within the first insulating material; and   a conductive layer formed over a surface of the semiconductor die and electrically connected to the first conductive via.   
     
     
         8 . The semiconductor device of  claim 7 , wherein the first width is less than half the second width. 
     
     
         9 . The semiconductor device of  claim 7 , wherein the first conductive via extends from the first insulating material. 
     
     
         10 . The semiconductor device of  claim 7 , wherein the first conductive via is recessed in the peripheral region. 
     
     
         11 . The semiconductor device of  claim 7 , further including a second conductive via formed in an active area of the semiconductor die, the second conductive via being electrically connected to the first conductive via. 
     
     
         12 . The semiconductor device of  claim 7 , further including a second insulating material disposed within the first conductive via. 
     
     
         13 . The semiconductor device of  claim 7 , further including a plurality of stacked semiconductor die electrically connected through the first conductive via. 
     
     
         14 . A semiconductor device, comprising:
 a semiconductor die;   an insulating material deposited in a peripheral region around the semiconductor die; and   a first conductive via formed partially through the insulating material, the first conductive via including different widths within the insulating material.   
     
     
         15 . The semiconductor device of  claim 14 , further including a conductive layer formed over a surface of the semiconductor die and electrically connected to the first conductive via. 
     
     
         16 . The semiconductor device of  claim 14 , wherein the different widths of the first conductive via include a first width less than half a second width. 
     
     
         17 . The semiconductor device of  claim 14 , wherein the first conductive via extends from the insulating material. 
     
     
         18 . The semiconductor device of  claim 14 , wherein the first conductive via is recessed in the peripheral region. 
     
     
         19 . The semiconductor device of  claim 14 , further including a second conductive via formed in an active area of the semiconductor die, the second conductive via being electrically connected to one of the first conductive via. 
     
     
         20 . The semiconductor device of  claim 14 , further including a plurality of stacked semiconductor die electrically connected through the first conductive vias. 
     
     
         21 . A semiconductor device, comprising:
 a semiconductor die;   a first insulating material deposited in a peripheral region around the semiconductor die;   a conductive via formed partially through the first insulating material, the conductive via including different widths within the first insulating material; and   a conductive layer formed over a surface of the semiconductor die and electrically connected to the conductive via.   
     
     
         22 . The semiconductor device of  claim 21 , wherein the different widths of the conductive via include a first width less than half a second width. 
     
     
         23 . The semiconductor device of  claim 21 , wherein the conductive via extends from the first insulating material. 
     
     
         24 . The semiconductor device of  claim 21 , wherein the conductive via is recessed in the peripheral region. 
     
     
         25 . The semiconductor device of  claim 21 , further including a second insulating material disposed within the conductive via.

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