Semiconductor circuit for electro-optical device and method of manufacturing the same
Abstract
In a monolithic active matrix circuit formed on a substrate, the active regions of at least a part of the thin film transistors (TFTs) constituting the peripheral circuit for driving the matrix region are added with a metal element for promoting the crystallization of silicon at a concentration of 1×10 16 to 5×10 19 cm −3 , no metal element is added to the active region of the TFTs for the matrix region. The channel forming regions of at least a part of the TFTs constituting the peripheral circuit and the channel forming regions of the TFTs for the matrix region are formed by a silicon semiconductor thin film having a monodomain structure.
Claims
exact text as granted — not AI-modified1 . A display device comprising:
a display portion comprising a plurality of pixels formed over a substrate; and a driver circuit formed over the substrate, the driver circuit comprising an inverter, wherein the inverter comprises an enhancement-type n-channel thin film transistor and a depletion-type n-channel thin film transistor, wherein a gate of the depletion-type n-channel thin film transistor is electrically connected to one of a source and a drain of the depletion-type n-channel thin film transistor, and wherein the one of the source and the drain of the depletion-type n-channel thin film transistor is electrically connected to one of a source and a drain of the enhancement-type n-channel thin film transistor.
2 . The display device according to claim 1 , wherein the depletion-type n-channel thin film transistor comprises a semiconductor layer, the semiconductor layer containing a metal element at a concentration of 1×10 16 to 5×10 19 cm −3 .
3 . The display device according to claim 1 , wherein each of the enhancement-type n-channel thin film transistor and the depletion-type n-channel thin film transistor comprises a semiconductor layer, the semiconductor layer comprising silicon.
4 . The display device according to claim 1 , wherein the display device is a liquid crystal device.
5 . The display device according to claim 1 ,
wherein the depletion-type n-channel thin film transistor comprises a semiconductor layer, and wherein the semiconductor layer is formed in a monodomain region which contains no grain boundary.
6 . A display device comprising:
a display portion comprising a plurality of pixels formed over a substrate; and a driver circuit formed over the substrate, the driver circuit comprising an inverter, wherein the inverter comprises a first enhancement-type n-channel thin film transistor and a second enhancement-type n-channel thin film transistor, wherein a gate of the first enhancement-type n-channel thin film transistor is electrically connected to one of a source and a drain of the first enhancement-type n-channel thin film transistor, and wherein the other one of the source and the drain of the first enhancement-type n-channel thin film transistor is electrically connected to one of a source and a drain of the second enhancement-type n-channel thin film transistor.
7 . The display device according to claim 6 , wherein the first enhancement-type n-channel thin film transistor comprises a semiconductor layer, the semiconductor layer containing a metal element at a concentration of 1×10 16 to 5×10 19 cm −3 .
8 . The display device according to claim 6 , wherein each of the first enhancement-type n-channel thin film transistor and a second enhancement-type n-channel thin film transistor comprises a semiconductor layer, the semiconductor layer comprising silicon.
9 . The display device according to claim 6 , wherein the display device is a liquid crystal device.
10 . The display device according to claim 6 .
wherein the first enhancement-type n-channel thin film transistor comprises a semiconductor layer, and wherein the semiconductor layer is formed in a monodomain region which contains no grain boundary.
11 . A display device comprising:
a first thin film transistor over a substrate; a pixel electrode electrically connected to the first thin film transistor; and a driver circuit formed over the substrate, the driver circuit comprising an inverter, wherein the inverter comprises an enhancement-type n-channel thin film transistor and a depletion-type n-channel thin film transistor, wherein a gate of the depletion-type n-channel thin film transistor is electrically connected to one of a source and a drain of the depletion-type n-channel thin film transistor, and wherein the one of the source and the drain of the depletion-type n-channel thin film transistor is electrically connected to one of a source and a drain of the enhancement-type n-channel thin film transistor.
12 . The display device according to claim 11 , wherein the depletion-type n-channel thin film transistor comprises a semiconductor layer, the semiconductor layer containing a metal element at a concentration of 1×10 16 to 5×10 19 cm −3 .
13 . The display device according to claim 11 , wherein each of the enhancement-type n-channel thin film transistor and the depletion-type n-channel thin film transistor comprises a semiconductor layer, the semiconductor layer comprising silicon.
14 . The display device according to claim 11 , wherein the display device is a liquid crystal device.
15 . The display device according to claim 11 ,
wherein the depletion-type n-channel thin film transistor comprises a semiconductor layer, and wherein the semiconductor layer is formed in a monodomain region which contains no grain boundary.Join the waitlist — get patent alerts
Track US2012268681A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.