Wafer Level Chip Scale Package Method Using Clip Array

Abstract

A method for wafer level chip scale package comprises providing a wafer with semiconductor chips formed thereon, forming a groove alongside each chip, providing a wafer size clip array with a plurality of clip contact areas each extending to a down set connecting bar, connecting the plurality of clip contact areas to a plurality of the electrodes disposed on a top surface of the chips with down set connecting bars disposed inside the grooves, encapsulating top of wafer in molding compound, thinning the bottom portion of the wafer and dicing the thin wafer into single chip packages. The chip has source and gate electrodes on a top surface connected to a first and second clip contact areas extending to a first a second down set connecting bars respectively, with the bottom surfaces of the down set connecting bars substantially coplanar to a drain electrode located at the chip bottom surface.

1 . A method for wafer level chip scale package comprises:
 providing a wafer with a top portion and a bottom portion; wherein the top portion of wafer comprises a semiconductor chip formed thereon with a plurality of top electrode contact areas disposed on a top surface of the semiconductor chip and a groove disposed along side the semiconductor chip on the top portion of the wafer;   providing a clip having a plurality of clip contact areas corresponding to the plurality of top electrode contact areas of the semiconductor chip; each clip contact area extend and contacted to a down set connecting bar;   displacing the clip on top of the wafer with the plurality of clip contact areas electrically connected to the plurality of the top electrode contact areas on the semiconductor chip;   wherein each of the down set connecting bars disposed within the groove; and   providing a molding material to encapsulate the top portion of the wafer and at lease a portion of the clip, wherein the molding material substantially filling the groove.   
     
     
         2 . The method for wafer level chip scale package of  claim 1  further comprise thinning the bottom portion of the wafer until a bottom surface of each of the down set connecting bar exposed on the bottom of the wafer. 
     
     
         3 . The method for wafer level chip scale package of  claim 1  further comprise thinning the bottom portion of the wafer until a bottom surface of each of the down set connecting bar exposed and substantially coplanar to the bottom of the wafer. 
     
     
         4 . The method for wafer level chip scale package of  claim 3  further comprise forming a metal layer on the bottom surface of the wafer. 
     
     
         5 . The method for wafer level chip scale package of  claim 4  wherein the semiconductor chip further comprises a bottom electrode dispose on the bottom portion of the wafer. 
     
     
         6 . The method for wafer level chip scale package of  claim 1  wherein at least one top electrode contact area is patterned into a plurality of subareas. 
     
     
         7 . The method for wafer level chip scale package of  claim 1  wherein at least one clip contact area is patterned into a plurality of subareas. 
     
     
         8 . The method for wafer level chip scale package of  claim 1  further comprises dicing the semiconductor chip from the wafer to form a wafer level chip scale package. 
     
     
         9 . The method for wafer level chip scale package of  claim 1  wherein the groove on the top portion of the wafer completely encircles the semiconductor chip. 
     
     
         10 . The method for wafer level chip scale package of  claim 1  wherein the groove on the top portion of the wafer extends downward through the bottom of the wafer. 
     
     
         11 . A wafer level chip scale package comprises:
 a semiconductor chip having a first electrode and a second electrode on a top surface and a third electrode on a bottom surface;   a clip having a first clip contact area connected to the first electrode and a second clip contact area connected to the second electrode, wherein the first clip contact area extending and connecting to a first down set connecting bar and the second clip contact area extending and connecting to a second down set connecting bar, wherein the first and second connecting bars being disposed away from an edge of the semiconductor chip and having bottom surfaces substantially coplanar to the bottom surface of the semiconductor chip.   
     
     
         12 . The wafer level chip scale package of  claim 11  further comprises:
 A molding material encapsulating the semiconductor chip and the clip, wherein the bottom surface of the semiconductor chip and the bottom surfaces of the first and second down set connecting bars exposed through the molding material encapsulation.