Chip package and method for forming the same

Abstract

An embodiment of the invention provides a chip package which includes: a first chip; a second chip disposed on the first chip, wherein a side surface of the second chip is a chemically-etched surface; and a bonding bulk disposed between the first chip and the second chip such that the first chip and the second chip are bonded with each other.

1 . A chip package, comprising:
 a first chip;   a second chip disposed on the first chip, wherein a side surface of the second chip is a chemically-etched surface; and   a bonding bulk disposed between the first chip and the second chip such that the first chip and the second chip are bonded with each other.   
     
     
         2 . The chip package as claimed in  claim 1 , wherein the first chip has a thickness larger than that of the second chip. 
     
     
         3 . The chip package as claimed in  claim 1 , wherein a side surface of the first chip is a diced surface. 
     
     
         4 . The chip package as claimed in  claim 1 , wherein the side surface of the second chip has a roughness smaller than that of a side surface of the first chip. 
     
     
         5 . The chip package as claimed in  claim 1 , wherein the side surface of the second chip has a roughness larger than that of a side surface of the first chip. 
     
     
         6 . The chip package as claimed in  claim 1 , wherein a side surface of the first chip is a chemically-etched surface. 
     
     
         7 . The chip package as claimed in  claim 1 , wherein a side surface of the bonding bulk closest to the side surface of the second chip is coplanar with the side surface of the second chip. 
     
     
         8 . The chip package as claimed in  claim 1 , wherein a side surface of the bonding bulk closest to the side surface of the second chip is not coplanar with the side surface of the second chip. 
     
     
         9 . The chip package as claimed in  claim 1 , wherein a width of the first chip is larger than that of the second chip. 
     
     
         10 . The chip package as claimed in  claim 1 , further comprising:
 a protecting layer disposed on the second chip; and   a conducting bump disposed on the second chip and penetrating the protection layer to electrically connect to a conducting region on the second chip.   
     
     
         11 . A method for forming a chip package, comprising:
 providing a first substrate;   providing a second substrate;   forming at least a bonding bulk on an upper surface of the first substrate and/or on a lower surface of the second substrate;   bonding the second substrate onto the first substrate through the bonding bulk;   forming a first protection layer on an upper surface of the second substrate, wherein the first protection layer has an opening exposing a predetermined scribe region of the second substrate;   using the first protection layer as a mask to etch and remove a portion of the second substrate located in the predetermined scribe region to form a through-hole exposing the first substrate; and   partially removing the first substrate exposed by the through-hole to form at least one chip package.   
     
     
         12 . The method for forming a chip package as claimed in  claim 11 , wherein the step of partially removing the first substrate exposed by the through-hole to form at least one chip package comprises using a dicing blade to cut through the first substrate. 
     
     
         13 . The method for forming a chip package as claimed in  claim 12 , wherein a width of the dicing blade is smaller than that of the predetermined scribe region. 
     
     
         14 . The method for forming a chip package as claimed in  claim 11 , wherein the step of partially removing the first substrate exposed by the through-hole to form at least one chip package comprises using an etching process to remove the exposed first substrate such that the first substrate is divided into a plurality of sections. 
     
     
         15 . The method for forming a chip package as claimed in  claim 11 , wherein the bonding bulk extends into the predetermined scribe region. 
     
     
         16 . The method for forming a chip package as claimed in  claim 11 , wherein the bonding bulk does not extend into the predetermined scribe region. 
     
     
         17 . The method for forming a chip package as claimed in  claim 11 , wherein a side surface of the bonding bulk is coplanar with a boundary of the predetermined scribe region. 
     
     
         18 . The method for forming a chip package as claimed in  claim 11 , further comprising:
 forming a second protection layer on the second substrate, wherein the second protection layer has an opening exposing a conducting region on the second substrate; and   forming a conducting bump on the exposed conducting region.   
     
     
         19 . The method for forming a chip package as claimed in  claim 18 , wherein the steps of forming the second protection layer and the conducting bump are performed after the step of etching and removing a portion of the second substrate is performed and before the step of partially removing the first substrate exposed by the through-hole to form at least one chip package is performed. 
     
     
         20 . The method for forming a chip package as claimed in  claim 11 , further comprising removing the first protection layer after the through-hole is formed.