Dual metal gate corner

Abstract

In view of the foregoing, disclosed herein are embodiments of an improved field effect transistor (FET) structure and a method of forming the structure. The FET structure embodiments each incorporate a unique gate structure. Specifically, this gate structure has a first section above a center portion of the FET channel region and second sections above the channel width edges (i.e., above the interfaces between the channel region and adjacent isolation regions). The first and second sections differ (i.e., they have different gate dielectric layers and/or different gate conductor layers) such that they have different effective work functions (i.e., a first and second effective work-function, respectively). The different effective work functions are selected to ensure that the threshold voltage at the channel width edges is elevated.

1 . A method of forming a field effect transistor, said method comprising:
 providing a substrate;   forming, on said substrate, a semiconductor body and an isolation region positioned laterally adjacent to a sidewall of said semiconductor body; and   forming a gate structure traversing a width of a channel region of said semiconductor body and further extending laterally beyond said sidewall onto said isolation region,   said forming of said gate structure comprising forming said gate structure with a first section, having a first effective work-function, above a center portion of said channel region and a second section, having a second effective work function different from said first effective work-function, above said sidewall.   
     
     
         2 . The method according to  claim 1 , said first effective work-function of said first section and said second effective work function of said second section ensure that a second threshold voltage at said sidewall is at least equal to a first threshold voltage at said center portion. 
     
     
         3 . The method according to  claim 1 , said forming of said gate structure comprising:
 forming a gate dielectric layer that traverses said width of said channel region and further extends laterally beyond said sidewall onto said isolation region;   forming, on said gate dielectric layer above said center portion of said channel region, a first gate conductor layer; and   forming, on said gate dielectric layer above said sidewall, a second gate conductor layer different from said first gate conductor layer.   
     
     
         4 . The method according to  claim 3 , said forming of said first gate conductor layer and said forming of said second gate conductor layer comprising:
 depositing a first metal;   patterning said first metal such that said first metal remains above said center portion only;   depositing a second metal that has a different work function than said first metal; and   patterning said second metal such that said second metal remains on said first metal and on said gate dielectric layer above said sidewall.   
     
     
         5 . The field effect transistor according to  claim 3 , said forming of said first gate conductor layer and said forming of said second gate conductor layer comprising:
 depositing a metal;   patterning said metal such that said metal remains above said center portion only;   depositing a doped polysilicon; and   patterning said doped polysilicon such that said doped polysilicon remains on said metal and on said gate dielectric layer above said sidewall.   
     
     
         6 . The method according to  claim 1 , said forming of said gate structure comprising:
 forming, above said center portion of said channel region, a first gate dielectric layer;   forming, above said sidewall adjacent to said first gate dielectric layer, a second gate dielectric layer different from said first gate dielectric layer, said first gate dielectric layer and said second gate dielectric layer having different fixed charge contents; and   forming a gate conductor layer on said first gate dielectric layer and on said second gate dielectric layer.   
     
     
         7 . The method according to  claim 6 , said forming of said first gate dielectric layer comprising using a first high-k dielectric material and said forming of said second gate dielectric layer comprising using a second high-k dielectric material different from said first high-k dielectric material. 
     
     
         8 . A method of forming a field effect transistor, said method comprising:
 providing a substrate;   forming, on said substrate, a semiconductor body and an isolation region positioned laterally adjacent to a sidewall of said semiconductor body; and   forming a gate structure traversing a width of a channel region of said semiconductor body and further extending laterally beyond said sidewall onto said isolation region,   said forming of said gate structure comprising forming said gate structure with a first section above a center portion of said channel region and a second section above said sidewall such that said first section and said second section have different gate dielectric layers and different gate conductor layers.   
     
     
         9 . The method according to  claim 8 , said forming of said gate structure comprising forming said gate structure so that said first section has a first effective work-function and said second section has a second effective work function different from said first effective work-function in order to ensure that a second threshold voltage at said sidewall is at least equal to a first threshold voltage at said center portion. 
     
     
         10 . The method according to  claim 8 , said forming of said gate structure comprising:
 forming a first gate dielectric layer that traverses said width of said channel region and further extends laterally beyond said sidewall onto said isolation region;   forming, above said center portion on said first gate dielectric layer, a first gate conductor layer;   forming, on said first gate dielectric layer above said sidewall, a second gate dielectric layer different from said first gate dielectric layer and having a different fixed charge content than said first gate dielectric layer; and   forming, on said second dielectric layer and on said first gate conductor layer, a second gate conductor layer different from said first gate conductor layer.   
     
     
         11 . The method according to  claim 10 , wherein said forming of said first gate conductor layer comprises using a first metal and said forming of said second gate conductor layer comprises using a second metal different from said first metal. 
     
     
         12 . The method according to  claim 10 , wherein said forming of said first gate conductor layer comprises using a metal and said forming of said second gate conductor layer comprises using a doped polysilicon. 
     
     
         13 . The method according to  claim 10 , wherein said forming of said first gate dielectric layer comprises using a first high-k dielectric material and said forming of said second gate dielectric layer comprises using a second high-k dielectric material different from said first high-k dielectric material. 
     
     
         14 . A field effect transistor comprising:
 a substrate;   a semiconductor body on said substrate, said semiconductor body comprising a channel region with a sidewall, a center portion and an edge portion between said sidewall and said center portion;   an isolation region on said substrate positioned laterally adjacent to said sidewall; and   a gate structure traversing a width of said channel region over said center portion and said edge portion and further extending laterally beyond said sidewall onto said isolation region,   said gate structure comprising a first section above said center portion and a second section above said edge portion and said sidewall,   said first section having a first gate dielectric layer above and immediately adjacent to said center portion and further having a first gate conductor layer above and immediately adjacent to said first gate dielectric layer,   said second section having a second gate dielectric layer different from said first gate dielectric layer above and immediately adjacent to said edge portion and extending laterally over said sidewall,   said second section further having a portion of a second gate conductor above and immediately adjacent to said second gate dielectric layer such that said first section has a first effective work-function and said second section has a second effective work function that is different from said first effective work-function, and   at least one of said first gate conductor layer and said second gate conductor layer comprising a metal.   
     
     
         15 . The field effect transistor according to  claim 14 , said first section having said first effective work-function and said second section having said second effective work function such that a second threshold voltage at said sidewall is at least equal to a first threshold voltage at said center portion. 
     
     
         16 . The field effect transistor according to  claim 14 , first gate conductor layer comprising a first metal and said second gate conductor layer comprising a second metal different from said first metal. 
     
     
         17 . The field effect transistor according to  claim 14 , said second gate conductor layer further having another portion that is above and immediately adjacent to said first gate conductor layer. 
     
     
         18 . The field effect transistor according to  claim 9 , said first gate conductor layer comprising said metal and said second gate conductor layer comprising a doped polysilicon. 
     
     
         19 . The field effect transistor according to  claim 9 , said first gate dielectric layer and said second gate dielectric layer comprising different high-k gate dielectric layers with different fixed charge contents. 
     
     
         20 . The field effect transistor according to  claim 9 , said second gate dielectric layer comprising multiple gate dielectric layers stacked.