Soi device having an increasing charge storage capacity of transistor bodies and method for manufacturing the same
Abstract
An SOI device includes an SOI substrate having a stacked structure including a buried oxide layer and a first silicon layer sequentially stacked on a silicon substrate. The SOI substrate possesses grooves having a depth that extends from an upper surface of the first silicon layer to a partial depth of the buried oxide layer. An insulation layer is formed on the lower surfaces of the grooves and a second silicon layer is formed filling the grooves having the insulation layer formed thereon. Gates are formed on the second silicon layer and junction regions are formed in the first silicon layer on both sides of the gates to contact the insulation layer.
Claims
exact text as granted — not AI-modified1 . An SOI device comprising:
an SOI substrate having a stacked structure including a buried oxide layer and a first silicon layer sequentially stacked on a silicon substrate and the SOI substrate having grooves defined therein whose depth extends from an upper surface of the first silicon layer to a partial depth of the buried oxide layer, wherein the partial depth of the buried oxide layer is less than that of a thickness of the buried oxide layer, wherein each of the grooves has a bulbous-shaped section by forming the grooves using a vertical shaped groove and a substantially spherical shaped groove that is mated to a lower end of the vertical shaped groove; an insulation layer formed only on a lower end of the vertical shaped groove, wherein the insulation layer is only on the lower end of the vertical shaped groove because a spacer on an upper end of the vertical shaped groove prevents the insulation layer from being formed on the upper end of the vertical shaped groove; a second silicon layer as a body of the SOI device formed to fill the grooves that have the insulation layer formed therein; gates formed on the second silicon layer; and junction regions formed in the first silicon layer on both sides of the gates to contact the insulation layer and the buried oxide layer, such as the second silicon layer is floated by the presence of the junction regions and the buried oxide layer.
2 . The SOI device according to claim 1 , wherein the vertical shaped groove is defined in an upper portion of the first silicon layer, and the substantially spherical shaped groove is defined in a lower portion of the first silicon layer and a portion of the buried oxide layer beneath the vertical shaped groove.
3 . The SOI device according to claim 1 , wherein the insulation layer comprises an oxide layer.
4 . The SOI device according to claim 1 , wherein the second silicon layer comprises an epi-silicon layer.Join the waitlist — get patent alerts
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