Thin film transistor and display device

Abstract

A thin film transistor that includes an oxide semiconductor film forming a channel, a gate electrode disposed on one side of the oxide semiconductor film via a gate insulating film and a pair of electrodes formed as a source region and a drain region.

1 . A thin film transistor comprising:
 an oxide semiconductor film forming a channel;   a gate electrode disposed on one side of the oxide semiconductor film via a gate insulating film; and   a pair of electrodes formed as a source region and a drain region, the source and drain regions in contact with a side surface of the oxide semiconductor film.   
     
     
         2 . A thin film transistor comprising an oxide semiconductor film forming a channel, wherein the oxide semiconductor film comprises a compound, InMZnO, where M represents Ga, Al or Fe. 
     
     
         3 . The thin film transistor according to  claim 1 , wherein the source and drain regions are a multilayer film, the multilayer film including at least a first layer, a second layer and a third layer,
 wherein,
 the first layer includes Mo, 
 the second layer includes Al, and 
 the third layer includes Ti. 
   
     
     
         4 . The thin film transistor according to  claim 3 , wherein the first layer includes Mo nitride or Mo silicon nitride. 
     
     
         5 . The thin film transistor according to  claim 3 , wherein at least one of the first, second, and/or third layer includes a metal having an oxygen barrier. 
     
     
         6 . The thin film transistor according to  claim 3 , wherein the second layer has a thickness greater than a thickness of each of the first and third layers. 
     
     
         7 . The thin film transistor according to  claim 3 , wherein the first layer has a thickness in the range from and including 30 to 50 nm. 
     
     
         8 . The thin film transistor according to  claim 3 , wherein the second layer has a thickness in the range from and including 300 to 1000 nm. 
     
     
         9 . The thin film transistor according to  claim 3 , wherein the third layer has a thickness in the range from and including 30 to 50 nm. 
     
     
         10 . The thin film transistor according to  claim 3 , wherein the second layer includes Al or Cu. 
     
     
         11 . The thin film transistor according to  claim 1 , wherein the gate insulator comprises silicon oxide, silicon nitride, silicon oxide nitride, or aluminum oxide. 
     
     
         12 . The thin film transistor according to  claim 1  further comprising a channel protection layer on the channel. 
     
     
         13 . The thin film transistor according to  claim 1 , wherein an anneal process is performed after the source and drain region are formed.