Double data rate test interface and architecture

Abstract

A device test architecture and a reduced device test interface enable efficient testing of embedded cores and other circuits within devices. The reduced device test interface uses a double data rate (DDR) signaling technique between the tester and the device. The DDR test interface allows the tester to interface to test circuits within the device, such as IEEE 1500 and/or IEEE 1149.1 test circuits, to provide high test data bandwidth to the test circuits using a minimum of test interface signals. The test architecture includes compare circuits that compare test response data within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester.

1 . An integrated circuit test architecture comprising:
 A. cores of functional circuitry;   B. test wrapper architectures, each test wrapper architecture being connected with one core;   C. test access mechanisms, each test access mechanism being connected with one of the test wrapper architectures;   D. test access port circuits, each test access port circuit being embedded in one of the cores;   E. a test access mechanism controller having a test access mechanism interface bus connected with each of the test wrapper architectures, the test access mechanisms, and the test access ports, the test access mechanism controller having a scan data input and a scan data output, and the test access mechanism controller having an enable output lead coupled to each test wrapper architecture, test access mechanism and test access port circuit; and   F. double data rate circuitry, the double data rate circuitry having a double data rate parallel data bus input of six leads, a double data rate clock input, a clock output connected to the controller, a load instruction register output connected to the controller, three mode outputs connected to the controller, and eight parallel data bus outputs connected to the controller and coupled to the test wrapper architectures, the test access mechanisms, and the test access ports.   
     
     
         2 . The integrated circuit of  claim 1  in which the interface bus includes a wrapper clock lead, a select wrapper instruction register lead, a shift wrapper lead, a capture wrapper lead, an update wrapper lead, a transfer wrapper lead, a wrapper reset lead, a wrapper serial input lead, and a wrapper serial output lead. 
     
     
         3 . The integrated circuit of  claim 1  in which each wrapper architecture includes:
 A. a wrapper control interface having a wrapper clock input, a select wrapper instruction register input, a shift wrapper input, a capture wrapper input, an update wrapper input, a transfer wrapper input, a wrapper reset input, and control outputs; 
 B. a wrapper serial input and a wrapper serial output; 
 C. a wrapper instruction register connected to the wrapper serial input, selectively coupled to the wrapper serial output, and connected to the control outputs; 
 D. a wrapper bypass register connected to the wrapper serial input, selectively coupled to the wrapper serial output, and connected to the control outputs; 
 E. wrapper boundary registers connected to inputs and outputs of the functional circuits, connected to the wrapper serial input, selectively coupled to the wrapper serial output, and connected to the control outputs; and 
 F. data register scan paths connected to the functional circuits, connected to the wrapper serial input, selectively coupled to the wrapper serial output, and connected to the control outputs.