Fault tolerant redundant clock circuit

Abstract

A clock generation circuit, includes, in part, a comparator, a logic unit, and a switching circuit. The switching circuit generates a signal that is applied to the comparator. If the input voltage level of the signal applied to the comparator is greater than a first reference voltage, the comparator asserts its first output signals. If the input voltage level of the signal applied to the comparator is less than a second reference voltage, the comparator asserts its second output signal. The output signals of the comparator form a first pair of feedback signals applied to the switching circuit. The logic unit responds to the output signals of the comparator to generate a second pair of oscillating feedback signals that are also applied to the switching circuit. The switching circuit varies a capacitor voltage in response to a reference current and in response to the two pairs of feedback signals it receives.

1 - 10 . (canceled) 
     
     
         11 . A clock generation circuit comprising:
 a first comparator responsive to a first input signal, said first comparator being adapted to change a first output signal when the first input signal is detected as being greater than a first reference, and further to change a second output signal when the first input signal is detected as being smaller than a second reference;   a first logic unit responsive to the first comparator and adapted to generate a a clock signal in response to the first and second output signals; and   a first switching circuit adapted to vary the first input signal in response to the first and second output signals and the clock signal.   
     
     
         12 . The clock generation circuit of  claim 11  further comprising:
 a current source adapted to supply a reference current to the first switching circuit; and 
 a capacitor adapted to charge, discharge or float in response to first switching circuit. 
 
     
     
         13 . The clock generation circuit of  claim 12  wherein said capacitor is disposed between the current source and the comparator. 
     
     
         14 . The clock generation circuit of  claim 11  further comprising:
 a second comparator responsive to a second input signal, said second comparator being adapted to change a third output signal when the second input signal is detected as being greater than a third reference, and further to change a fourth output signal when the second input signal is detected as being smaller than a fourth reference; 
 a second switching circuit adapted to vary the second input signal in response to the third and fourth output signals and the clock signal; 
 a third comparator responsive to a third input signal, said third comparator being adapted to change a fifth output signal when the third input signal is detected as being greater than a fifth reference, and further to change a sixth output signal when the third input signal is detected as being smaller than a sixth reference; 
 a third switching circuit adapted to vary the third input signal in response to the fifth and sixth output signals and the clock signal; 
 said logic unit being responsive to the third, fourth, fifth and sixth output signals. 
 
     
     
         15 . The clock generation circuit of  claim 14  further comprising first and second voters responsive to the first, second and third comparators. 
     
     
         16 . The clock generation circuit of  claim 14  wherein each of said first, second and third switching circuits comprises first, second, third, fourth, fifth and sixth transistor, said first transistor receiving a reference current at a first terminal and a first one of a pair of complementary clock signals at its second input terminal, said second transistor receiving the reference current at a first terminal and a second one of the pair of complementary clock signals at its second input terminal, said third transistor having a first terminal coupled to a third terminal of the first transistor and a second terminal receiving a first output signal of an associated comparator, said fourth transistor having a first terminal coupled to a third terminal of the second transistor and a second terminal receiving a second output signal of the associated comparator, said fifth transistor having first and second terminals coupled to a third terminal of the third transistor, and a third terminal coupled to a voltage supply or ground, said sixth transistor having a first terminal coupled to a third terminal of the fourth transistor, a second terminal coupled to the second terminal of the fifth transistor and a third terminal coupled to the voltage supply or ground. 
     
     
         17 . A clock generation circuit comprising:
 N clock generators each comprising:   a comparator adapted to compare an input signal to each of M reference signals and to assert M output signals in response;   a switching circuit responsive to an associated comparator's M output signals and to a pair of oscillating feedback signals, said switching circuit adapted to generate the input signal in response;   M voters responsive to the M output signals of the N comparators; and   a logic unit responsive to the voters and generating the pair of oscillating feedback signals in response.   
     
     
         18 . An electronic system comprising:
 a functional circuit having an input, and output and a clock input;   a clock generation circuit, coupled to the clock input of the functional circuit, the clock generation circuit comprising:
 a comparator responsive to a first input signal, said comparator being adapted to change a first signal when the first input signal is detected as being greater than a first reference, and further to change a second signal when the first input signal is detected as being smaller than a second reference; 
 a first logic unit responsive to the comparator and adapted to generate a clock signal in response to the first and second signals; and 
 a first switching circuit adapted to vary the first signal in response to the first and second signals and the clock signal.