US2012260103A1PendingUtilityA1
Security circuit using at least two finite state machine units and methods using the same
Est. expiryFeb 22, 2025(expired)· nominal 20-yr term from priority
H04L 9/06G11C 8/20G11C 8/16G11C 8/18
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Claims
Abstract
A security circuit using at least two finite state machine units for storing data to and reading data from a multiport memory in a pipelined manner and an intermediate memory, for facilitating transfer of data between the at least two finite state machines. The security circuit may be used to perform key setup and/or data ciphering faster. The security circuit may operate in any environment where the key is changed every frame, for example, a wireless LAN application and the security circuit may operate in conjunction with, or as part of, a MAC controller.
Claims
exact text as granted — not AI-modified1 .- 30 . (canceled)
31 . A security circuit, comprising:
a read finite state machine unit configured to read the data from the multiport memory in the pipelined manner and output the data to the intermediate memory; a write finite state machine unit configured to receive the data from the intermediate memory and write the data to the multiport memory in the pipelined manner; and an intermediate memory configured to facilitate transfer of data between the read finite state and the write finite state machine unit.Join the waitlist — get patent alerts
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