Contemporaneous margin verification and memory access for memory cells in cross point memory arrays

Abstract

Circuitry for restoring data values in re-writable non-volatile memory is disclosed. An integrated circuit includes a memory access circuit and a sensing circuit configured to sense a data signal during a read operation to at least one two-terminal non-volatile cross-point memory array. Each memory array includes a plurality of two-terminal memory elements. A plurality of the memory arrays can be fabricated over the substrate and vertically stacked on one another. Further, the integrated circuit can include a margin manager circuit configured to manage a read margin for the two-terminal memory elements substantially during the read operation, thereby providing for contemporaneous read and margin determination operations. Stored data read from the two-terminal memory elements may have a value of the stored data restored (e.g., re-written to the same cell or another cell) if the value is not associated with a read margin (e.g., a hard programmed or hard erased state).

1 . A margin verification method for a re-writable, non-volatile memory comprising:
 selecting at least one memory element of a non-volatile memory array for a read operation;   providing a reference signal;   sensing the reference signal and a leakage signal of the selected memory element during a first cycle of the read operation;   sensing a read current from the selected memory elements of the array and the leakage signal during a second cycle of the read operation;   generating a data signal indicative of stored data in the selected memory elements;   managing a read margin for selected memory elements substantially during the first and second cycles; and   determining if a value of the data signal is within a specified level of the read margin.   
     
     
         2 . The method of  claim 1  including re-writing the stored data to the selected memory elements to restore the read margin to the specified level of the read margin. 
     
     
         3 . The method of  claim 1  and further comprising determining whether the value of the stored data is within a first range of resistance values that specify the read margin for the selected memory elements. 
     
     
         4 . The method of  claim 3  and wherein the first range of resistance values are indicative of a hard state for the stored data. 
     
     
         5 . The method of  claim 4  and wherein the hard state comprises a hard programmed state for the stored data if the data signal is indicative of a value of zero, or a hard erased state for the stored data if the data signal is indicative of a value of one. 
     
     
         6 . The method of  claim 1  including determining whether the value of the stored data is associated with a second range of resistance values that specify the read margin for the selected memory elements. 
     
     
         7 . The method of  claim 6  wherein the second range of resistance values are indicative of a soft state for the stored data. 
     
     
         8 . The method of  claim 7  wherein the soft state comprises a soft programmed state for the stored data if the data signal is indicative of a value of zero, or a soft erased state for the stored data if the data signal is indicative of a value of one. 
     
     
         9 . The method of  claim 7  including restoring the read margin for selected memory elements by changing an association of the selected memory elements from the second range of resistance values to a first range of resistance values. 
     
     
         10 . The method of  claim 1  including managing the read margin as a function of time. 
     
     
         11 . The method of  claim 1  including providing a capacitance element, and, during the second cycle, determining a rate of current flow to or from the capacitance element as indicative of whether the read margin for selected memory elements is associated with a specified level of read margin. 
     
     
         12 . The method of  claim 1  wherein the reference signal comprises a reference current. 
     
     
         13 . The method of  claim 12  including providing the reference current from a reference memory cell of the array. 
     
     
         14 . The method of  claim 1  wherein the leakage signal comprises leakage currents generated by a subset of the plurality of memory elements that are not selected for the read operation. 
     
     
         15 . The method of  claim 1  including repeating the sensing steps at selected sample times to form sequential sensing samples, and storing the sequential sensing samples in a sample repository. 
     
     
         16 . The method of  claim 15  including determining whether a memory cell requires restoration based on the sequential sensing samples. 
     
     
         17 . The method of  claim 1  wherein each memory element is configured to store at least two-bits of data, and the method includes managing read margins for multi-level cells (MLC). 
     
     
         18 . The method of  claim 1  wherein the memory array comprises a stack of multiple layers of memory elements. 
     
     
         19 . The method of  claim 1  wherein the memory array comprises a two-terminal cross-point array of resistive memory cells. 
     
     
         20 . The method of  claim 1  including providing a capacitance element coupled to at least one of the selected memory elements, and, during the second cycle, determining a rate of current flow to or from the capacitance element by sampling a voltage of the capacitance element to form a profile as indicative of the read margin.