Attenuator

Abstract

An attenuator includes a first node, a second node, a first circuit coupled between the first and second nodes, a second circuit coupled between the first circuit and the second node, and coupled to the first circuit via a third node, a third circuit coupled to the third node, and a variable capacitor coupled to the third node and configured to regulate an attenuation characteristic of the attenuator such that a flat attenuation characteristic can be achieved within a predetermined frequency range.

1 . An attenuator comprising:
 a first node;   a second node;   a first circuit coupled between said first and second nodes;   a second circuit coupled between said first circuit and said second node, and coupled to said first circuit via a third node;   a third circuit coupled to said third node; and   a variable capacitor coupled to the third node and configured to regulate an attenuation characteristic of the attenuator such that a flat attenuation characteristic is achievable within a predetermined frequency range.   
     
     
         2 . The attenuator according to claim I, wherein the first circuit includes a field effect transistor comprising a gate terminal coupled to a resistor. 
     
     
         3 . The attenuator according to  claim 1 , wherein a second circuit includes a second field effect transistor comprising another gate terminal coupled to another resistor, and
 wherein the resistor and the another resistor are coupled to different nodes respectively.   
     
     
         4 . The attenuator according to  claim 1 , further comprising a capacitor coupled between said first node and said first circuit. 
     
     
         5 . The attenuator according to  claim 4 , further comprising another capacitor coupled between said second circuit and said second node. 
     
     
         6 . The attenuator according to  claim 1 , wherein the third circuit includes yet another field effect transistor comprising yet another gate terminal coupled to yet another resistor. 
     
     
         7 . A circuit comprising:
 a first node;   a second node;   a third node between the first and second nodes;   a first field effect transistor coupled between said first and third nodes;   a second field effect transistor coupled to the third node comprising a second gate terminal coupled to a second resistor;   a third field effect transistor coupled to the third node comprising a third gate terminal coupled to a third resistor;   a first capacitor coupled to the second field effect transistor; and   a second capacitor coupled to the third field effect transistor;   
     
     
         8 . The circuit according to  claim 7 , further comprising a third capacitor coupled between the second and third nodes. 
     
     
         9 . The circuit according to  claim 8 , further comprising a fourth field effect transistor coupled between the second and third nodes. 
     
     
         10 . The circuit according to  claim 7 , further comprising;
 a fifth field effect transistor coupled to the third node comprising a fifth gate terminal coupled to fifth resistor; and   a fourth capacitor coupled to the fifth field effect transistor.