Semiconductor memory device which includes memory cell having charge accumulation layer and control gate

Abstract

A semiconductor memory device includes a memory cell array, a power source circuit, a sense amplifier, a control circuit, and a processor. The memory cell array includes a nonvolatile memory cell. The power source circuit includes a first register and generates a voltage. The sense amplifier includes a second register, reads from the memory cell and amplifies the read data. The control circuit includes a third register and controls operations of the power source circuit and the sense amplifier. The processor controls the operations of the power source circuit, the sense amplifier and the control circuit by giving an instruction to the first to third registers. The control circuit decodes the instruction received at the third register so as to control the power source circuit and the sense amplifier directly based on a result of decoding.

1 . A memory system comprising:
 a microcomputer;   a power source circuit including a first resister, an AND gate, and a flip-flop connected to the first resister and the AND gate;   a switch circuit;   a control circuit including a second resistor, the second register being connected to the switch circuit;   wherein the microcomputer sends first data to the first resister, and   second data from the second resistor and a clock are input to the AND gate.   
     
     
         2 . The memory system according to  claim 1 , wherein the microcomputer sends third data to the switch circuit. 
     
     
         3 . The memory system according to  claim 1 , wherein the switch circuit includes a selection circuit to which a third data is input from the microcomputer and sending the third data to the second resistor. 
     
     
         4 . The memory system according to  claim 2 , wherein a first signal is input to the first resistor. 
     
     
         5 . The memory system according to  claim 4 , wherein the switch circuit includes an OR gate to which the first signal is input and outputting an operation result to the second resistor. 
     
     
         6 . The memory system according to  claim 5 , wherein the third data is (M+N) bits (M, N are natural numbers) and the second data is M-bit of the third data. 
     
     
         7 . The memory system according to  claim 6 , wherein the second resistor sends N-bit of the third data to a control decoder. 
     
     
         8 . The memory system according to  claim 6 , wherein the N-bit of the third data is a control signal of the power source circuit, and
 the M-bit of the second data is update timing information of the power source circuit.   
     
     
         9 . The memory system according to  claim 6 , wherein the first data corresponds to a set value of a voltage to be generated by the power source circuit. 
     
     
         10 . The memory system according to  claim 4 , wherein when the first signal is in “H” level, the first resister sends the first data to the flip-flop. 
     
     
         11 . The memory system according to  claim 10 , wherein when the M-bit is in “H” level, the flip-flop sends the first data to the digital-analog converter. 
     
     
         12 . The memory system according to  claim 6 , wherein when the M-bit is in “H” level, the power source circuit operates based on the first data. 
     
     
         13 . The memory system according to  claim 12 , wherein a second signal is input to the second resistor. 
     
     
         14 . The memory system according to  claim 13 , wherein when the second signal is in “H” level, the operation of the power source circuit based on the first data terminates.