Display apparatus and method of manufacturing the same

Abstract

A display apparatus includes a substrate and a plurality of pixels disposed on the substrate. Each pixel includes a gate electrode on the substrate, a common electrode insulated from the gate electrode on the substrate, a first insulating layer covering the gate electrode and the common electrode, a semiconductor pattern disposed on the first insulating layer to overlap with the gate electrode, source and drain electrodes disposed on the semiconductor pattern and spaced apart from each other, and a pixel electrode disposed on the first insulating layer to cover the drain electrode and form an electric field with the common electrode. The display apparatus may be manufactured by first to fourth photolithography processes using first to fourth masks, and the first mask may be a slit mask or a diffraction mask.

1 . A display apparatus comprising:
 a substrate; and   a plurality of pixels disposes on the substrate, wherein each pixel comprises:   a gate electrode disposed on the substrate;   a common electrode disposed on the substrate and insulated from the gate electrode;   a first insulating layer covering the gate electrode and the common electrode;   a semiconductor pattern disposed on the first insulating layer to overlap with the gate electrode;   a source electrode disposed on the semiconductor pattern;   a drain electrode disposed on the semiconductor pattern and spaced apart from the source electrode; and   a pixel electrode disposed on the first insulating layer to cover the drain electrode and configured to form an electric field with the common electrode.   
     
     
         2 . The display apparatus of  claim 1 , further comprising a passivation layer, wherein the semiconductor pattern comprises a channel portion corresponding to an area between the source electrode and the drain electrode and having an upper surface that is exposed, and the passivation layer covers the channel portion. 
     
     
         3 . The display apparatus of  claim 2 , wherein the gate electrode comprises:
 a first conductive layer comprising a first conductive material and disposed on the substrate; and   a second conductive layer comprising a second conductive material and disposed on the first conductive layer.   
     
     
         4 . The display apparatus of  claim 3 , wherein the common electrode comprises the first conductive material. 
     
     
         5 . The display apparatus of  claim 4 , wherein the first conductive material comprises at least one of indium tin oxide, indium zinc oxide, and an indium tin zinc oxide. 
     
     
         6 . The display apparatus of  claim 2 , further comprising:
 a plurality of gate lines disposed on the substrate and extended in a first direction; and   a plurality of data lines extended in a second direction crossing the first direction, wherein the first insulating layer is interposed between the gate lines and the data lines, wherein each of the pixels is connected to an adjacent gate line and an adjacent data line.   
     
     
         7 . The display apparatus of  claim 6 , wherein the substrate comprises a display area in which the pixels are arranged to display an image and a pad area positioned adjacent to at least one side of the display area, and further comprises a gate pad disposed in the pad area and connected to one of the gate lines and a data pad disposed in the pad area and connected to one of the data lines. 
     
     
         8 . The display apparatus of  claim 7 , wherein the gate pad further comprises:
 a first gate pad part comprising a first conductive material and disposed on the substrate; and   a second gate pad part comprising a second conductive material and disposed on the first gate pad part, the second gate pad part being provided with a first opening to expose a portion of the first gate pad part.   
     
     
         9 . The display apparatus of  claim 8 , wherein the data pad further comprises:
 a first data pad part disposed on the substrate; and   a second data pad part disposed on the first data pad and provided with a second opening to expose a portion of the first data pad part.   
     
     
         10 . The display apparatus of  claim 9 , wherein the first data pad part comprises a same material as the pixel electrode and the second data pad part comprises a same material as the passivation layer. 
     
     
         11 . The display apparatus of  claim 1 , wherein the pixel electrode comprises a trunk portion and a plurality of branch portions protruded from the trunk portion and spaced apart from each other. 
     
     
         12 . A method of manufacturing a display apparatus, comprising:
 performing a first photolithography process using a first mask to form a first wire pattern including a gate line, a gate electrode, and a common electrode on a substrate;   forming an insulating layer on the substrate to cover the first wire pattern;   performing a second photolithography process using a second mask to form a second wire pattern including a data line and a thin film transistor electrode pattern on the insulating layer;   performing a third photolithography process using a third mask to form a third wire pattern including a source electrode, a drain electrode, and a pixel electrode on the substrate and form a channel portion between the source electrode and the drain electrode; and   performing a fourth photolithography process using a fourth mask to form a passivation layer that covers the channel portion.   
     
     
         13 . The method of  claim 12 , wherein the first mask is at least one of a slit mask and a diffraction mask. 
     
     
         14 . The method of  claim 13 , wherein the first photolithography process comprises:
 sequentially depositing a first conductive material and a second conductive material on the substrate to form a first conductive layer and a second conductive layer; and   etching a portion of the first conductive layer and a portion of the second conductive layer using the first mask.   
     
     
         15 . The method of  claim 14 , wherein the etching of the first and second conductive layers comprises:
 forming a photoresist layer on the second conductive layer;   exposing and developing the photoresist layer using the at least one of the slit mask and the diffraction mask to form a first photoresist layer pattern having a first thickness in a first region and a second photoresist layer having a second thickness smaller than the first thickness in a second region different from the first region;   etching a portion of the first photoresist layer pattern and a portion of the second photoresist layer pattern using the first and second photoresist layer patterns as a mask;   ashing the first and second photoresist layer patterns to form a third photoresist layer pattern having a third thickness smaller than the first thickness in the first region; and   etching the second conductive layer using the third photoresist layer pattern as a mask to form the gate line and the gate electrode in the first region and the common electrode in the second region.   
     
     
         16 . The method of  claim 12 , wherein the second photolithography process comprises:
 sequentially forming a first semiconductor layer including amorphous silicon or polycrystalline silicon, a second semiconductor layer including amorphous silicon doped with a dopant or polycrystalline silicon doped with the dopant, and a third semiconductor layer including a third conductive material on the insulating layer; and   etching the first semiconductor layer, the second semiconductor layer, and the third conductive layer using the second mask to form an active layer, an ohmic contact pattern, and a semiconductor electrode pattern.   
     
     
         17 . The method of  claim 16 , wherein the third photolithography process is to each a portion of the ohmic contact pattern and a portion of the semiconductor electrode pattern using the third mask to form the source electrode, the drain electrode spaced apart from the source electrode, and the channel portion. 
     
     
         18 . The method of  claim 12 , wherein the substrate comprises a display area in which the pixels are arranged to display an image and a pad area positioned adjacent to at least one side of the display area, and the first photolithography process further comprises forming a gate pad disposed in the pad area and connected to the gate line. 
     
     
         19 . The method of  claim 18 , wherein the forming of the gate pad comprises:
 forming a first gate pad part on the substrate; and   forming a second gate pad part on the first gate pad part, the second gate pad part including a first opening to expose a portion of an upper surface of the first gate pad part.   
     
     
         20 . The method of  claim 19 , wherein the first gate pad part is formed of the first conductive material and the second gate pad part is formed of the second conductive material. 
     
     
         21 . The method of  claim 18 , wherein the third photolithography process further comprises forming a first data pad part disposed in the pad area and connected to the data line, and the fourth photolithography process further comprises forming a second data pad part disposed on the first data pad part and including a second opening to expose a portion of an upper surface of the first data pad part. 
     
     
         22 . The method of  claim 21 , wherein the second data pad part is formed of a same material as the passivation layer.