Semiconductor device and method of manufacturing the same

Abstract

According to one embodiment, a semiconductor device includes interconnects extending from a element formation area to the drawing area, and connected with semiconductor elements in the element formation area and connected with contacts in the drawing area. The interconnects are formed based on a pattern of a (n+1) th second sidewall film matching a pattern of a n th (where n is an integer of 1 or more) first sidewall film on a lateral surface of a sacrificial layer. A first dimension matching an interconnect width of the interconnects and an interconnects interval in the element formation area is (k1/2 n )×(λ/NA) or less when an exposure wavelength of an exposure device is λ, a numerical aperture of a lens of the exposure device is NA and a process parameter is k1. A second dimension matching an interconnect interval in the drawing area is greater than the first dimension.

1 . A semiconductor device comprising:
 a semiconductor substrate which includes an element formation area and a drawing area;   a plurality of semiconductor elements which are provided in the element formation area;   a plurality of interconnects which extend from the element formation area to the drawing area, and which are connected with the semiconductor elements; and   a plurality of contacts which are provided in the drawing area and are connected respectively with the plurality of interconnects,   wherein   the interconnects are formed based on a pattern of a (n+1) th  second sidewall film matching a pattern of a n th  (where n is an integer of 1 or more) first sidewall film on a lateral surface of a sacrificial layer,   a first dimension matching an interconnect width of the interconnects and an interval between the interconnects adjacent in the element formation area is smaller than a limit dimension of resolution of lithography,   the first dimension is (k1/2 n )×(λ/NA) or less when an exposure wavelength of an exposure device is λ, a numerical aperture of a lens of the exposure device is NA and a process parameter is k1, and   a second dimension matching an interval between the interconnects adjacent in the drawing area is greater than the first dimension.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein a dimension of the contacts is greater than the first dimension. 
     
     
         3 . The semiconductor device according to  claim 1 , wherein an interval between the contacts connected to adjacent interconnects is greater than the first dimension. 
     
     
         4 . The semiconductor device according to  claim 1 , wherein the semiconductor element is a field-effect transistor including a charge storage layer and a control gate electrode. 
     
     
         5 . The semiconductor device according to  claim 4 , wherein
 the interconnects are word lines as the control gate electrode, and   the interconnects are embedded in recesses formed based on the pattern of the (n+1) th  second sidewall film.   
     
     
         6 . The semiconductor device according to  claim 1 , wherein, in case of n=1, the first dimension is 19 nm or less, and the second dimension is greater than 30 nm. 
     
     
         7 . A method of the semiconductor device comprising:
 forming a first sidewall film including a first line width smaller than a limit dimension of resolution of lithography by a n th  (n is an integer of 1 or more) sidewall formation process, on a lateral surface of a sacrificial layer in an element formation area and a drawing area of a semiconductor substrate;   forming a first mask including a second line width greater than the first line width on the first sidewall film in the drawing area by lithography after the sacrificial layer is removed;   forming a plurality of second sidewall films including a third line width which is the first line width or less, by a (n+1) sidewall formation process on a lateral surface of a first pattern based on the first sidewall film and the first mask; and   processing a processing target layer on the semiconductor substrate using the second sidewall film as a mask, and forming a plurality of interconnects which comprise at least one of a first interconnect width and an first interconnect interval including a first dimension smaller than a limit dimensions of resolution of lithography in the element formation area, and which comprise a second interconnect interval including a second dimension greater than the first dimension in the drawing area.   
     
     
         8 . The method of the semiconductor device according to  claim 7 , further comprising:
 forming second masks including a fourth line width greater than the third line width to cover the second sidewall films in the drawing area by lithography after the first pattern is removed; and   processing the processing target layer in the element formation area based on the second sidewall film, and, simultaneously, processing the processing target layer in the drawing area based on the second mask and forming contacts including a third dimension greater than the first dimension and connected to the interconnects.   
     
     
         9 . The method of a semiconductor device according to  claim 8 , wherein an interval between the adjacent contacts is greater than the first dimension. 
     
     
         10 . The method of the semiconductor device according to  claim 7 , further comprising
 processing the processing target layer and, simultaneously, processing a first layer below the processing target layer based on the second sidewall film and forming a semiconductor element connected with the interconnects.   
     
     
         11 . The method of a semiconductor device according to  claim 10 , wherein
 the semiconductor element is a field-effect transistor including a charge storage layer and a control gate electrode,   the interconnects are word lines as the control gate, and   the processed first layer is the charge storage layer.   
     
     
         12 . The method of a semiconductor device according to  claim 7 , wherein
 a plurality of recesses are formed in the processing target layer based on the second sidewall film, and   the interconnects are embedded in the recess in a self-aligning manner.   
     
     
         13 . The method of a semiconductor device according to  claim 12 , wherein
 recesses in which the interconnect are embedded are formed at portions matching spaces between the adjacent second sidewall films in the processing target layer, and   recesses in which contacts are embedded are formed at portions matching the first mask in the processing target layer.   
     
     
         14 . The method of a semiconductor device according to  claim 12 , wherein
 the recesses of respectively independent patterns are formed by processing the processing target layer after a third mask is formed on one end of the second sidewall films in the drawing area without covering a portion matching the first mask.   
     
     
         15 . The method of a semiconductor device according to  claim 12 , wherein
 each of the interconnects formed in recesses in the processing target layer are word lines as a control gate electrode of a field-effect transistor including a charge storage layer.   
     
     
         16 . The method of a semiconductor device according to  claim 12 , wherein
 interconnects formed in recesses in the processing target layer are bit lines connected to a field-effect transistor including a charge storage layer and a control gate electrode.   
     
     
         17 . The method of a semiconductor device according to  claim 7 , wherein
 when an exposure wavelength of an exposure device is λ, a numerical aperture of a lens of the exposure device is NA and a process parameter is k1,   the first dimension is less than or equal to (k1/2 n )×(λ/NA) and   the second dimension is greater than (k1/2 n )×(λ/NA).   
     
     
         18 . A method of a semiconductor device comprising:
 forming a plurality of adjacent sacrificial layers on a first processing target layer in an element formation area and a drawing area of a semiconductor substrate, the sacrificial layers comprising first line patterns including a first line width in the element formation area and first projection patterns of a second line width greater than the first line width in the drawing area, the first line patterns being adjacent at a first interval and the projecting patterns being adjacent at a second interval greater than the first interval;   forming first sidewall films including a third line width smaller than a limit dimension of resolution of lithography by a n th  (where n is an integer of 1 or more) sidewall formation process, on lateral surfaces of the sacrificial layers;   processing the first processing target layer using the first sidewall film as a mask after the plurality of sacrificial layers are removed, forming a first pattern including the third line width in the element formation area and forming a second pattern including a fourth line width greater than the third line width in the drawing area based on a difference in etching bias between the first interval and the second interval;   forming a second sidewall film including a fifth line width which is the third line width or less, by a (n+1) th  sidewall formation process on lateral surfaces of the first pattern and the second pattern; and   processing a second processing target layer using the second sidewall film as a mask after the first and second patterns are removed, forming a plurality of interconnects which comprise at least one of a first interconnect width and an first interconnect interval including a first dimension smaller than a limit dimensions of resolution of lithography in the element formation area, and which comprise a second interconnect interval including a second dimension greater than the first dimension in the drawing area.   
     
     
         19 . The method of the semiconductor device according to  claim 18 , further comprising:
 forming a first mask including a sixth line width greater than the fifth line width to cover the second sidewall film in the drawing area by lithography after the first pattern is removed; and   processing the second processing target layer in the element formation area based on the second sidewall film and, simultaneously, processing the second processing target layer in the drawing area based on the first mask and forming in the drawing area a contact which includes a third dimension greater than the first dimension and is connected to the interconnects.   
     
     
         20 . The method of the semiconductor device according to  claim 19 , wherein
 an interval between the adjacent contacts is greater than the first dimension.