Thin film transistor

Abstract

A thin film transistor (TFT) and a fabricating method thereof are provided. The TFT includes a channel layer, an ohmic contact layer, a dielectric layer, a source, a drain, a gate, and a gate insulating layer. The channel layer has an upper surface and a sidewall. The ohmic contact layer is disposed on a portion of the upper surface of the channel layer. The dielectric layer is disposed on the sidewall of the channel layer, and does not overlap with the ohmic contact layer. The source and the drain are disposed on portions of the ohmic contact layer and the dielectric layer. A portion of dielectric layer is not covered by the source or the drain. The gate is above or below the channel layer. The gate insulating layer is disposed between the gate and the channel layer.

1 . A thin film transistor disposed on a substrate, the thin film transistor comprising:
 a channel layer having an upper surface and a sidewall;   an ohmic contact layer disposed on a portion of the upper surface of the channel layer;   a dielectric layer disposed on the sidewall of the channel layer, wherein the dielectric layer and ohmic contact are not overlapped;   a source and a drain disposed on the ohmic contact layer and on a portion of the dielectric layer, and a portion of the dielectric layer is not covered by the source or the drain;   a gate disposed above or below the channel layer; and   a gate insulating layer disposed between the gate and the channel layer.   
     
     
         2 . The thin film transistor as claimed in  claim 1 , wherein the gate insulating layer is disposed on the substrate to cover the gate and the dielectric layer extends from the sidewall of the channel layer to the substrate when the gate is below the channel layer. 
     
     
         3 . The thin film transistor as claimed in  claim 2 , further comprising a passivation layer covering the source, the drain, the dielectric layer, and the channel layer. 
     
     
         4 . The thin film transistor as claimed in  claim 1 , wherein the gate insulating layer covers the source, the drain, the dielectric layer, and a portion of the channel layer when the gate is above the channel layer. 
     
     
         5 . The thin film transistor as claimed in  claim 4 , further comprising passivation layer covering the gate and the gate insulating layer. 
     
     
         6 . The thin film transistor as claimed in  claim 4 , further comprising a buffer layer between the dielectric layer and the substrate and between the channel layer and the substrate.