Fabrication of RRAM Cell Using CMOS Compatible Processes

Abstract

Generally, the subject matter disclosed herein relates to the fabrication of an RRAM cell using CMOS compatible processes. A resistance random access memory device is disclosed which includes a semiconducting substrate, a top electrode, at least one metal silicide bottom electrode formed at least partially in the substrate, wherein at least a portion of the at least one bottom electrode is positioned below the top electrode, and at least one insulating layer positioned between the top electrode and at least a portion of the at least one bottom electrode. A method of making a resistance random access memory device is disclosed that includes forming an isolation structure in a semiconducting substrate to thereby define an enclosed area, performing at least one ion implantation process to implant dopant atoms into the substrate within the enclosed area, after performing the at least one ion implantation process, forming a layer of refractory metal above at least portions of the substrate, and performing at least one heat treatment process to form at least one metal silicide bottom electrode at least partially in the substrate, wherein at least a portion of the at least one bottom electrode is positioned below at least a portion of a top electrode of the device.

1 . A resistance random access memory device, comprising:
 a semiconducting substrate;   a metal silicide top electrode positioned above said substrate;   a single metal silicide bottom electrode formed at least partially in said substrate, wherein at least a portion of said single bottom electrode is positioned below an entire width of said top electrode; and   at least one insulating layer positioned between said top electrode and said single bottom electrode.   
     
     
         2 . The device of  claim 1 , wherein said top electrode and said single bottom electrode are made of the same metal silicide material. 
     
     
         3 . The device of  claim 1 , wherein said top electrode and said single bottom electrode are made of different metal silicide materials. 
     
     
         4 . The device of  claim 1 , wherein said single bottom electrode is bounded by an isolation structure positioned in said substrate that surrounds said device. 
     
     
         5 . A resistance random access memory device, comprising:
 a semiconducting substrate;   a metal silicide top electrode positioned above said substrate;   two separated metal silicide bottom electrodes formed at least partially in said substrate, wherein at least a portion of each of said two bottom electrodes is positioned below separate portions of said top electrode; and   at least one insulating layer positioned between said portions of said top electrode and said at least said portion of each of said two bottom electrodes.   
     
     
         6 . The device of  claim 5 , wherein said top electrode and each of said two bottom electrodes are made of nickel silicide. 
     
     
         7 . The device of  claim 5 , wherein said two bottom electrodes are bounded by an isolation structure positioned in said substrate that surrounds said device. 
     
     
         8 . The device of  claim 5 , wherein said at least one insulating layer is comprised of a single layer of a high-k dielectric material. 
     
     
         9 . A method of making a resistance random access memory device comprising a top electrode, comprising:
 forming an isolation structure in a semiconducting substrate to thereby define an enclosed area;   performing at least one ion implantation process to implant dopant atoms into said substrate within said enclosed area;   after performing said at least one ion implantation process, forming a layer of refractory metal above at least portions of said substrate; and   performing at least one heat treatment process to form at least one metal silicide bottom electrode at least partially in said substrate, wherein at least a portion of said at least one bottom electrode is positioned below at least a portion of said top electrode.   
     
     
         10 . The method of  claim 9 , wherein said dopant atoms are arsenic. 
     
     
         11 . The method of  claim 9 , wherein said top electrode and said at least one bottom electrode are made of nickel silicide. 
     
     
         12 . The method of  claim 9 , wherein said at least one bottom electrode comprises two bottom electrodes that are separated from one another, wherein at least a portion of each of said two bottom electrodes is positioned below a portion of said top electrode. 
     
     
         13 . The method of  claim 9 , wherein said at least one bottom electrode is a single bottom electrode. 
     
     
         14 . The method of  claim 13 , wherein a portion of said single bottom electrode is positioned under an entire width of said top electrode. 
     
     
         15 . The method of  claim 14 , wherein said single bottom electrode is bounded by an isolation structure in said substrate that surrounds said device. 
     
     
         16 . A method of making a resistance random access memory device comprising a top electrode, comprising:
 forming an isolation structure in a semiconducting substrate to thereby define an enclosed area;   forming said top electrode for said device above said enclosed area;   after forming said top electrode, performing at least one ion implantation process to implant dopant atoms into said substrate within said enclosed area;   after performing said at least one ion implantation process, forming a layer of refractory metal above said top electrode and at least portions of said substrate; and   performing at least one heat treatment process to form at least one metal silicide bottom electrode at least partially in said substrate, wherein at least a portion of said at least one bottom electrode is positioned below at least a portion of said top electrode.   
     
     
         17 . The method of  claim 16 , wherein said top electrode and said at least one bottom electrode are made of nickel silicide. 
     
     
         18 . The method of  claim 16 , wherein said at least one bottom electrode comprises two bottom electrodes that are separated from one another, wherein at least a portion of each of said two bottom electrodes is positioned below a portion of said top electrode. 
     
     
         19 . The method of  claim 16 , wherein said at least one bottom electrode is a single bottom electrode. 
     
     
         20 . The method of  claim 19 , wherein a portion of said single bottom electrode is positioned under an entire width of said top electrode. 
     
     
         21 . The method of  claim 20 , wherein said single bottom electrode is bounded by an isolation structure in said substrate that surrounds said device. 
     
     
         22 . An array of resistance random access memory device, comprising:
 a semiconducting substrate;   at least first and second resistance random memory devices formed in and above said substrate, each of said resistance random memory devices comprising two separated metal silicide bottom electrodes formed at least partially in said substrate; and   a common top electrode structure that is electrically and operatively coupled to each of said separated metal silicide bottom electrodes.   
     
     
         23 . The array of  claim 22  wherein at least a portion of each of said two bottom electrodes is positioned below separate portions of said common top electrode. 
     
     
         24 . The array of  claim 23  further comprising at least one insulating layer positioned between said portions of said common top electrode and said at least said portion of each of said two bottom electrodes. 
     
     
         25 . The array of  claim 1 , wherein said memory array defines a 2×2 memory cell. 
     
     
         26 . The array of  claim 1 , wherein said memory array defines a 2×3 memory cell. 
     
     
         27 . The array of  claim 1 , wherein said memory array defines a 3×3 memory cell.