US2012241196A1PendingUtilityA1
Circuit board and method of manufacturing same
Est. expiryMar 22, 2031(~4.7 yrs left)· nominal 20-yr term from priority
Inventors:Tao Wang
H05K 2201/09681H05K 1/0259H05K 3/386Y10T29/49156
46
PatentIndex Score
0
Cited by
0
References
0
Claims
Abstract
A circuit board includes a substrate and a conductor layer disposed on the substrate. The conductor layer includes conducting wires and gapped electrostatic protected areas (EPAs) forming a reticulated pattern and electrically isolated from the conducting wires. The manner and method of construction of the circuit board reduces warping and bulging, to induce more reliable component connections. A method for manufacturing the circuit board is also provided.
Claims
exact text as granted — not AI-modified1 . A circuit board comprising:
a substrate; and a conductor layer disposed on the substrate, the conductor layer comprising a plurality of conducting wires and a plurality of electrostatic protected areas (EPAs) electrically isolated from the plurality of conducting wires, wherein each of the EPAs comprises a plurality of openings.
2 . The circuit board of claim 1 , wherein the openings are arranged in a matrix.
3 . The circuit board of claim 2 , wherein each of the openings is square.
4 . The circuit board of claim 3 , wherein a size of each of the openings is in the range from 1 mm×1 mm to 3 mm×3 mm.
5 . The circuit board of claim 3 , wherein a distance separating two adjacent openings is approximately 1 mm.
6 . The circuit board of claim 1 , wherein the conductor layer further comprises a plurality of gaps, the gaps separating the conducting wires from the EPAs.
7 . The circuit board of claim 1 , further comprising an adhesive layer between the conductor layer and the substrate, the adhesive layer adhering the conductor layer to the substrate.
8 . The circuit board of claim 7 , wherein the openings pass through the conductor layer and adhesive layer.
9 . The circuit board of claim 8 , further comprising an insulating layer disposed on the conductor layer, wherein the insulating layer comprises a plurality of holes.
10 . The circuit board of claim 9 , wherein the holes are configured to allow connection between pins of electronic components disposed on the circuit board and corresponding of the conducting wires of the conductor layer.
11 . A method of manufacturing a circuit board, the method comprising:
providing a substrate covered with a conducting layer; and forming a conductor layer by etching the conducting layer, the conductor layer comprising a plurality of conducting wires, a plurality of electrostatic protected areas (EPAs) electrically isolated from the plurality of conducting wires, and a plurality of openings in each of the EPAs.
12 . The method of claim 11 , wherein the openings are arranged in a matrix.
13 . The method of claim 12 , wherein each of the openings is square.
14 . The method of claim 13 , wherein a size of each of the openings is in the range from 1 mm×1 mm to 3 mm×3 mm.
15 . The method of claim 13 , wherein a distance separating two adjacent openings is approximately 1 mm.
16 . The method of claim 11 , further comprising adhering the conducting layer to the substrate via an adhesive layer.
17 . The method of claim 16 , wherein the openings pass through the conductor layer and adhesive layer.
18 . The method of claim 11 , further comprising directly bonding the conducting layer to the substrate.
19 . The method of claim 11 , further comprising providing an insulating layer on the conductor layer.
20 . The method of claim 15 , further comprising forming a plurality of holes in the insulating layer, wherein the holes are configured to allow connection between pins of electronic components disposed on the circuit board and corresponding of the conducting wires of the conductor layer.Join the waitlist — get patent alerts
Track US2012241196A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.