Liquid crystal display device

Abstract

To suppress a malfunction of a circuit due to deterioration in a transistor. In a transistor which continuously outputs signals having certain levels (e.g., L-level signals) in a pixel or a circuit, the direction of current flowing through the transistor is changed (inverted). That is, by changing the level of voltage applied to a first terminal and a second terminal (terminals serving as a source and a drain) every given period, the source and the drain are switched every given period. Specifically, in a portion which successively outputs signals having certain levels (e.g., L-level signals) in a circuit including a transistor, L-level signals having a plurality of different potentials (L-level signals whose potentials are changed every given period) are used as the signals having certain levels.

1 . A liquid crystal display device comprising:
 a first transistor;   a second transistor; and   a third transistor,   wherein one of a source and a drain of the first transistor is electrically connected to a first wiring, and the other of the source and the drain of the first transistor is electrically connected to a third wiring,   wherein one of a source and a drain of the second transistor is electrically connected to a second wiring, and the other of the source and the drain of the second transistor is electrically connected to the third wiring,   wherein a gate of the third transistor is electrically connected to the third wiring,   wherein the third transistor is turned on by a selection signal and is turned off by a non-selection signal,   wherein the selection signal is supplied from the first wiring to the third wiring in a period during which the first transistor is on,   wherein the non-selection signal is supplied from the second wiring to the third wiring in a period during which the second transistor is on, and   wherein at least one of the selection signal and the non-selection signal is a signal whose potential is changed every predetermined period.   
     
     
         2 . The liquid crystal display device according to  claim 1 , wherein the non-selection signal is a signal whose potential is changed at least in the period during which the second transistor is on. 
     
     
         3 . The liquid crystal display device according to  claim 1 , wherein the selection signal is a signal whose potential is changed at least in the period during which the first transistor is on. 
     
     
         4 . The liquid crystal display device according to  claim 1 , wherein one of a source and a drain of the third transistor is electrically connected to a pixel electrode. 
     
     
         5 . The liquid crystal display device according to  claim 1 , wherein each of the first transistor, the second transistor and the third transistor is a transistor in which one of amorphous silicon and microcrystalline silicon is used for a channel formation region. 
     
     
         6 . A liquid crystal display device comprising:
 a first transistor;   a second transistor;   a third transistor; and   a fourth transistor,   wherein one of a source and a drain of the first transistor is electrically connected to a first wiring, and the other of the source and the drain of the first transistor is electrically connected to a third wiring,   wherein one of a source and a drain of the second transistor is electrically connected to a second wiring, and the other of the source and the drain of the second transistor is electrically connected to the third wiring,   wherein one of a source and a drain of the fourth transistor is electrically connected to the second wiring, and the other of the source and the drain of the fourth transistor is electrically connected to the third wiring,   wherein a gate of the third transistor is electrically connected to the third wiring,   wherein the third transistor is turned on by a selection signal and is turned off by a non-selection signal,   wherein the selection signal is supplied from the first wiring to the third wiring in a period during which the first transistor is on,   wherein the non-selection signal is supplied from the second wiring to the third wiring in a period during which at least one of the second transistor and the fourth transistor is on, and   wherein at least one of the selection signal and the non-selection signal is a signal whose potential is changed every predetermined period.   
     
     
         7 . The liquid crystal display device according to  claim 6 , wherein the non-selection signal is a signal whose potential is changed at least in the period during which at least one of the second transistor and the fourth transistor is on. 
     
     
         8 . The liquid crystal display device according to  claim 6 , wherein the second transistor and the fourth transistor are alternately turned on and off in predetermined order. 
     
     
         9 . The liquid crystal display device according to  claim 6 , wherein a direction of current flowing through the second transistor is changed, and
 wherein a direction of current flowing through the fourth transistor is changed.   
     
     
         10 . The liquid crystal display device according to  claim 6 , wherein one of a source and a drain of the third transistor is electrically connected to a pixel electrode. 
     
     
         11 . The liquid crystal display device according to  claim 6 , wherein each of the first transistor, the second transistor and the third transistor is a transistor in which one of amorphous silicon and microcrystalline silicon is used for a channel formation region. 
     
     
         12 . A semiconductor device comprising:
 a first transistor;   a second transistor whose first terminal is electrically connected to a first terminal of the first transistor;   a third transistor whose first terminal is electrically connected to the first terminal of the first transistor;   a fourth transistor whose gate terminal is electrically connected to the first terminal of the first transistor,   wherein the first terminal of the first transistor is one of source and drain terminals of the first transistor,   wherein the first terminal of the second transistor is one of source and drain terminals of the second transistor,   wherein the first terminal of the third transistor is one of source and drain terminals of the third transistor, and   wherein at least one of the first transistor, the second transistor, the third transistor, and the fourth transistor comprises a semiconductor layer that comprise a channel formation region comprising an oxide semiconductor.   
     
     
         13 . The semiconductor device according to  claim 12 ,
 wherein a second terminal of the second transistor is electrically connected to a first line,   wherein a second terminal of the third transistor is electrically connected to a second line, and   wherein the first line and the second line are different lines.   
     
     
         14 . The semiconductor device according to  claim 12 , wherein the oxide semiconductor comprises indium, gallium, and zinc. 
     
     
         15 . The semiconductor device according to  claim 12 , further comprising:
 a pixel electrode electrically connected to a first terminal of the fourth transistor.   
     
     
         16 . The semiconductor device according to  claim 12 , further comprising:
 a pixel electrode electrically connected to a first terminal of the fourth transistor;   a counter electrode over the pixel electrode; and   a liquid crystal material between the pixel electrode and the counter electrode.   
     
     
         17 . The semiconductor device according to  claim 12 , further comprising:
 a source line electrically connected to a second terminal of the fourth transistor.   
     
     
         18 . The semiconductor device according to  claim 12 , further comprising at least one of the group consisting of a printed wiring board, a flexible printed circuit, a backlight unit, a light guide plate, a prism sheet, a diffusion sheet, a reflective sheet, a light source, and a cooling device. 
     
     
         19 . The semiconductor device according to  claim 12 , further comprising:
 a fifth transistor;   a sixth transistor whose first terminal is electrically connected to a first terminal of the fifth transistor;   a seventh transistor whose first terminal is electrically connected to the first terminal of the fifth transistor; and   an eighth transistor whose gate terminal is electrically connected to the first terminal of the fifth transistor,   wherein the first terminal of the fifth transistor is one of source and drain terminals of the fifth transistor,   wherein the first terminal of the sixth transistor is one of source and drain terminals of the sixth transistor,   wherein the first terminal of the seventh transistor is one of source and drain terminals of the seventh transistor,   wherein a second terminal of the second transistor, and a second terminal of the seventh transistor are electrically connected to each other, and   wherein a second terminal of the third transistor, and a second terminal of the sixth transistor are electrically connected to each other.   
     
     
         20 . A semiconductor device comprising:
 a first transistor;   a second transistor whose first terminal is electrically connected to a first terminal of the first transistor;   a third transistor whose first terminal is electrically connected to the first terminal of the first transistor;   a fourth transistor whose gate terminal is electrically connected to the first terminal of the first transistor;   a fifth transistor;   a sixth transistor whose first terminal is electrically connected to a first terminal of the fifth transistor;   a seventh transistor whose first terminal is electrically connected to the first terminal of the fifth transistor;   an eighth transistor whose gate terminal is electrically connected to the first terminal of the fifth transistor;   a ninth transistor;   a tenth transistor whose first terminal is electrically connected to a first terminal of the ninth transistor;   an eleventh transistor whose first terminal is electrically connected to the first terminal of the ninth transistor;   a twelfth transistor whose gate terminal is electrically connected to the first terminal of the ninth transistor;   wherein a second terminal of the second transistor, a second terminal of the seventh transistor, and a second terminal of the tenth transistor are electrically connected to one another,   wherein a second terminal of the third transistor, a second terminal of the sixth transistor, and a second terminal of the eleventh transistor are electrically connected to one another, and   wherein at least one of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor comprises a semiconductor layer that comprise a channel formation region comprising an oxide semiconductor.   
     
     
         21 . The semiconductor device according to  claim 20 ,
 wherein a second terminal of the second transistor is electrically connected to a first line,   wherein a second terminal of the third transistor is electrically connected to a second line, and   wherein the first line and the second line are different lines.   
     
     
         22 . The semiconductor device according to  claim 20 , wherein the oxide semiconductor comprises indium, gallium, and zinc. 
     
     
         23 . The semiconductor device according to  claim 20 , further comprising:
 a pixel electrode electrically connected to a first terminal of the fourth transistor.   
     
     
         24 . The semiconductor device according to  claim 20 , further comprising:
 a pixel electrode electrically connected to a first terminal of the fourth transistor;   a counter electrode over the pixel electrode; and   a liquid crystal material between the pixel electrode and the counter electrode.   
     
     
         25 . The semiconductor device according to  claim 20 , further comprising:
 a source line electrically connected to a second terminal of the fourth transistor.   
     
     
         26 . The semiconductor device according to  claim 20 , further comprising at least one of the group consisting of a printed wiring board, a flexible printed circuit, a backlight unit, a light guide plate, a prism sheet, a diffusion sheet, a reflective sheet, a light source, and a cooling device.