US2012235706A1PendingUtilityA1

High speed integrated circuit

Assignee: KAO RICHARD F CPriority: Jul 7, 2004Filed: Mar 13, 2012Published: Sep 20, 2012
Est. expiryJul 7, 2024(expired)· nominal 20-yr term from priority
Inventors:Richard Kao
H10W 90/756H10W 72/5449H10W 72/932H03K 19/018578H03K 19/0948
50
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Claims

Abstract

A novel driver circuit that uses a differential driver as a design backbone is described. Unlike a conventional differential interface, which typically has two or more outputs for providing an output signal and its complement, one of the differential driver's outputs is coupled to drive an output signal onto a signal line, while another one of the differential driver's outputs is unused and terminated, for instance by coupling the output to package ground or a voltage source via a capacitor. The performance of the driver circuit is significantly improved over conventional singled-ended driver designs.

Claims

exact text as granted — not AI-modified
1 . An integrated circuit comprising:
 a plurality of complementary logic gates, wherein each of said logic gates comprises a plurality of transistors, each of said plurality of transistors being configured without a current source.   
     
     
         2 . The integrated circuit according to  claim 1  wherein said plurality of complementary logic gates being configured to support an peak-to-peak output voltage of at least 2 Volts, and an output operating frequency of at least 600 MHz. 
     
     
         3 . The integrated circuit according to  claim 1 , wherein said plurality of logic gates comprises CMOS TTL circuits. 
     
     
         4 . The integrated circuit according to claim  136  being fabricated with 0.3 μm or larger semiconductor fabrication technology. 
     
     
         5 . The integrated circuit according to  claim 1 , wherein the plurality of complementary logic gates at least in part comprise a differential pre-driver circuit, wherein the differential pre-driver circuit comprise voltage mode differential logic gates. 
     
     
         6 . The integrated circuit according to  claim 1 , further comprising an output driver to receive complementary signals from the plurality of complementary logic gates. 
     
     
         7 . The integrated circuit according to  claim 6 , wherein the output driver comprises a HSTL output driver, a TTL output driver, a LVDS output driver, a LVPECL output driver, or a pair of inverters.

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