Data processing device and method of reading trimming data

Abstract

A data processing device including a nonvolatile memory comprising a plurality of memory regions in which a same trimming data is stored, and a trimming data read control circuit configured to read the trimming data from a random memory region. The trimming data read control circuit comprises a region selection signal generation circuit configured to generate a region selection signal that specifies a random memory region among the memory regions, and a read circuit configured to read the trimming data from the random one memory region in response to the region selection signal. The region selection signal generation circuit comprises a clock counter configured to count a clock signal until a reset signal is input, and a signal generation circuit configured to generate the region selection signal based on a count value of the clock counter. The reset signal is input to the clock counter at a random timing.

1 . A data processing device comprising:
 a nonvolatile memory comprising a plurality of memory regions in which a same trimming data is stored; and   a trimming data read control circuit configured to read said trimming data from a random one of the plurality of memory regions,   wherein the trimming data read control circuit comprises:
 a region selection signal generation circuit configured to generate a region selection signal that specifies a random one memory region among the plurality of memory regions; and 
 a read circuit configured to read the trimming data from the random one memory region in response to the region selection signal, 
   wherein the region selection signal generation circuit comprises:
 a clock counter configured to count a clock signal until a reset signal is input; and 
 a signal generation circuit configured to generate the region selection signal based on a count value of the clock counter, 
   wherein the reset signal is input to the clock counter at a random timing.   
     
     
         2 . The data processing device according to  claim 1 , wherein said plurality of memory regions are connected to different word lines, respectively. 
     
     
         3 . The data processing device according to  claim 2 , wherein said plurality of memory regions are connected to different bit lines, respectively. 
     
     
         4 . The data processing device according to  claim 1 , wherein the region selection signal generation circuit outputs the region selection signal to a word line connected to the random one of the plurality of memory regions. 
     
     
         5 . The data processing device according to  claim 1 , wherein, when the data processing device is powered on, the trimming data read control circuit randomly selects the random one of the plurality of memory regions. 
     
     
         6 . The data processing device according to  claim 1 , wherein the nonvolatile memory further comprises a memory cell array comprising a predetermined memory region, which comprises the plurality of memory regions in which the same trimming data is stored. 
     
     
         7 . The data processing device according to  claim 1 , wherein the nonvolatile memory further comprises the trimming data read control circuit. 
     
     
         8 . The data processing device according to  claim 1 , wherein the trimming data read control circuit is configured to randomly select the random one of the plurality of memory regions from which to read the trimming data. 
     
     
         9 . The data processing device according to  claim 1 , wherein the nonvolatile memory further comprises a plurality of word lines each connected to a different memory region of the plurality of memory regions, and
 wherein, when the trimming data read control circuit reads the trimming data from the random one of the plurality of memory regions, a read word line voltage is applied to a word line connected to the random one of the plurality of memory regions.   
     
     
         10 . The data processing device according to  claim 9 , wherein, when the read word voltage is applied to the word line connected to the random one the plurality of memory regions, the trimming data stored in each memory region of the plurality of memory regions other than the random one of the plurality of memory regions remain unaffected by the read word line voltage. 
     
     
         11 . The data processing device according to  claim 1 , wherein the clock counter comprises a first clock counter,
 wherein the clock signals comprises a first clock signal,   wherein the data processing device further comprises:
 a power supply detection circuit configured to monitor a power supply voltage to generate a voltage detection signal indicating that the power supply voltage is more than a predetermined voltage; and 
 a second clock counter configured to start to count a second clock signal in response to the voltage detection signal, 
   wherein the reset signal is generated by the second clock counter when a count value of the second clock counter becomes equal to a predetermined value.   
     
     
         12 . A data processing device comprising:
 a nonvolatile memory that comprises a plurality of memory regions in which a same trimming data is stored; and   a trimming data read control circuit that reads the trimming data from a random one of the plurality of memory regions,   wherein the trimming data read control circuit comprises:
 a first clock counter that starts to count a first clock signal in response to a power activation; and 
 a second signal generator that generates a region selection signal based on a count value of the first clock counter, 
   wherein the trimming data read controller reads the trimming data from the random one memory region in accordance with the region selection signal.   
     
     
         13 . The data processing device according to  claim 12 , wherein the first clock counter counts the first clock signal until a reset signal is input. 
     
     
         14 . The data processing device according to  claim 13 , wherein the reset signal is input to the first clock counter at a random timing. 
     
     
         15 . The data processing device according to  claim 13 , further comprising:
 a power supply detector that monitors a power supply voltage to generate a voltage detection signal indicating that the power supply voltage is more than a predetermined voltage; and   a second clock counter that stats to count a second clock signal in response to the voltage detection signal,   wherein the reset signal is generated by the second clock counter when a count value of the second clock counter becomes equal to a predetermined value.   
     
     
         16 . The data processing device according to  claim 15 , wherein the second clock counter stats to operate in response to power activation.