Pn floating gate non-volatile storage element

Abstract

Non-volatile storage elements having a PN floating gate are disclosed herein. The floating gate may have a P− region near the tunnel oxide, and may have an N+ region near the control gate. In some embodiments, a P− region near the tunnel oxide helps provide good data retention. In some embodiments, an N+ region near the control gate helps to achieve a good coupling ratio between the control gate and floating gate. Therefore, programming of non-volatile storage elements is efficient. Also erasing the non-volatile storage elements may be efficient. In some embodiments, having a P− region near the tunnel oxide (as opposed to a strongly doped p-type semiconductor) may improve erase efficiency relative to P+.

1 . A non-volatile storage element comprising:
 a channel region in a substrate;   a tunnel oxide over the channel region;   a floating gate having an interface to the tunnel oxide over the channel region, the floating gate having a first region formed from P semiconductor and a second region formed from N semiconductor, the first region substantially borders the interface to the tunnel oxide over the channel region;   a control gate; and   an inter-gate dielectric region between the floating gate and the control gate, the floating gate having an interface to the inter-gate dielectric region, the second region substantially borders the interface between the floating gate and the inter-gate dielectric.   
     
     
         2 . The non-volatile storage element of  claim 1 , wherein the first region is P− and the second region is N+. 
     
     
         3 . The non-volatile storage element of  claim 1 , further comprising:
 a barrier region between the first region and the second region of the floating gate, the barrier region impedes diffusion of impurities between the second region and the first region.   
     
     
         4 . The non-volatile storage element of  claim 3 , wherein the barrier region is an oxide that allows charge carriers to cross during operation of the non-volatile storage element. 
     
     
         5 . The non-volatile storage element of  claim 3 , wherein the barrier region is nitride that allows charge carriers to cross during operation of the non-volatile storage element. 
     
     
         6 . The non-volatile storage element of  claim 1 , further comprising:
 a region of intrinsic semiconductor between the first region and the second region of the floating gate.   
     
     
         7 . The non-volatile storage element of  claim 1 , wherein the channel region is an n-channel. 
     
     
         8 . A memory array comprising:
 a plurality of non-volatile storage elements over a substrate, each of the non-volatile storage elements including:   a tunnel oxide over the substrate;   a floating gate having an interface to the tunnel oxide, the floating gate having a first region formed from P− semiconductor and a second region formed from N+ semiconductor, the first region of the floating gate substantially borders the interface between the floating gate and the tunnel oxide;   a control gate that is over the second region of the floating gate; and   an inter-gate dielectric region between the floating gate and the control gate, the second region substantially borders the interface between the floating gate and the inter-gate dielectric.   
     
     
         9 . The memory array of  claim 8 , further comprising a plurality of transistors, each of the transistors having a gate, a channel, and a transistor tunnel oxide region over the channel, the gate having an N+ region at an interface to the transistor tunnel oxide region over the channel. 
     
     
         10 . The memory array of  claim 8 , further comprising:
 a barrier region between the first region and the second region of the floating gate, the barrier region inhibits diffusion of impurities between the second region and the first region and allows charge carriers to tunnel through during operation of the non-volatile storage element.   
     
     
         11 . The memory array of  claim 8 , further comprising:
 a region of intrinsic semiconductor between the first region and the second region of the floating gate.   
     
     
         12 . A method for forming a memory array comprising:
 forming insulator over a substrate, the insulator formed in one or more first regions for non-volatile storage elements and in one or more second regions for transistors;   forming a P− semiconductor region over the insulator in the one or more first regions and in the one or more second regions;   forming a first N+ semiconductor region over the P− semiconductor region in the one or more first regions and in the one or more second regions;   transforming the P− semiconductor region in the one or more second regions into a second N+ semiconductor region;   forming floating gates for non-volatile storage elements in the one or more first regions from the P− semiconductor region and the first N+ semiconductor region that remains in the one or more first regions; and   forming transistor gates in the one or more second regions, the transistor gates including at least the second N+ semiconductor region and the first N+ semiconductor region.   
     
     
         13 . The method of  claim 12 , further comprising:
 forming an inter-gate dielectric over the first N+ semiconductor region at least in the one or more first regions;   forming a third N+ semiconductor region over the inter-gate dielectric in the one or more first regions and in the one or more second regions; and   forming control gates for the non-volatile storage elements from the third N+ semiconductor region.   
     
     
         14 . The method of  claim 13 , wherein the forming transistor gates is performed after forming the third N+ semiconductor region, the transistor gates further including the third N+ semiconductor region. 
     
     
         15 . The method of  claim 12 , wherein the transforming the P− semiconductor region in the one or more second regions includes:
 counter-doping the P− semiconductor region in the one or more second regions with an N-type impurity to form the second N+ semiconductor region, the second N+ semiconductor region borders the insulator in the one or more second regions. 
 
     
     
         16 . The method of  claim 15 , further comprising:
 forming a barrier region over the P− semiconductor region in the one or more first regions, the barrier region impedes diffusion of impurities between the first N+ semiconductor region and the P− semiconductor region.   
     
     
         17 . The method of  claim 16 , further comprising:
 forming the barrier region over the P− semiconductor region in the one or more second regions, the counter-doping includes implanting the N-type impurity through the barrier region in the one or more second regions.   
     
     
         18 . The method of  claim 12 , further comprising:
 forming an intrinsic semiconductor region over the P− semiconductor region in the one or more first regions, the first N+ semiconductor region is formed over the intrinsic semiconductor region.   
     
     
         19 . The method of  claim 12 , wherein the transforming the P− semiconductor region in the one or more second regions includes:
 performing a thermal anneal to cause diffusion of N-type impurities from the first N+ semiconductor region into the P− semiconductor region in the one or more second regions. 
 
     
     
         20 . The method of  claim 19 , further comprising:
 forming a barrier region over the P− semiconductor region in the one or more first regions, the barrier region prevents diffusion of impurities between the first N-type semiconductor region and the P− semiconductor region in the one or more first regions.   
     
     
         21 . The method of  claim 12 , wherein the transistor gates include gates of select transistors in the memory array. 
     
     
         22 . The method of  claim 12 , wherein the transistor gates include gates of transistors in a peripheral region of the memory array. 
     
     
         23 . A method of forming a non-volatile storage element, the method comprising:
 forming a tunnel oxide region over a substrate;   forming source/drain regions in the substrate;   forming a floating gate over the tunnel oxide between the source/drain regions, the floating gate having an interface to the tunnel oxide between the source/drain regions, the floating gate having a first region formed from P semiconductor and a second region formed from N semiconductor, the first region substantially borders the interface between the floating gate and the tunnel oxide between the source/drain regions;   forming a control gate; and   forming an inter-gate dielectric region between the floating gate and the control gate, the floating gate having an interface to the inter-gate dielectric region, the second region substantially borders the interface to the inter-gate dielectric.   
     
     
         24 . The method of  claim 23 , wherein the first region is P− and the second region is N+. 
     
     
         25 . The method of  claim 23 , further comprising:
 forming a barrier region between the first region and the second region of the floating gate, the barrier region impedes diffusion of impurities between the second region and the first region.   
     
     
         26 . The method of  claim 23 , further comprising:
 forming a region of intrinsic semiconductor between the first region and the second region of the floating gate.