Semiconductor integrated circuit device having plural delay paths and controller capable of blocking signal transmission in delay path

Abstract

A semiconductor integrated circuit device, includes a plurality of delay paths which are connected in parallel between synchronous operation circuits operating in synchronism with a clock signal and which enable transmission of a signal, a delay detection unit that detects respective delay times in the plurality of delay paths, and a control unit that selects one delay path from the plurality of delay paths based on a detection result of the delay detection unit, and controls blocking of signal transmission in the delay paths other than the selected one delay path. The control unit selects, as one delay path, a delay path whose delay time is a middle value among the plurality of delay paths.

1 . A semiconductor integrated circuit device, comprising:
 a plurality of delay paths which are connected in parallel between synchronous operation circuits operating in synchronism with a clock signal and which enable transmission of a signal;   a delay detection unit that detects respective delay times in the plurality of delay paths; and   a control unit that selects one delay path from the plurality of delay paths based on a detection result of the delay detection unit, and controls blocking of signal transmission in the delay paths other than the selected one delay path, wherein the control unit selects, as one delay path, a delay path whose delay time is a middle value among the plurality of delay paths.   
     
     
         2 . A semiconductor integrated circuit device, comprising:
 a plurality of delay paths which are connected in parallel between synchronous operation circuits operating in synchronism with a clock signal and which enable transmission of a signal;   
       a delay detection unit that detects respective delay times in the plurality of delay paths;
 a control unit that selects one delay path from the plurality of delay paths based on a detection result of the delay detection unit, and controls blocking of signal transmission in the delay paths other than the selected one delay path, 
 wherein the control unit selects, as one delay path, a delay path whose delay time is a minimum value among the plurality of delay paths, and 
 wherein the control unit reduces a power supply voltage in the selected one delay path down to a predetermined voltage. 
 
     
     
         3 . A semiconductor integrated circuit device, comprising:
 a plurality of delay paths which are connected in parallel between synchronous operation circuits operating in synchronism with a clock signal and which enable transmission of a signal;   a delay detection unit that detects respective delay times in the plurality of delay paths;   a control unit that selects one delay path from the plurality of delay paths based on a detection result of the delay detection unit, and controls blocking of signal transmission in the delay paths other than the selected one delay path,   wherein the control unit selects, as one delay path, a delay path whose delay time is a minimum value among the plurality of delay paths, and   wherein the control unit selects one delay path in correspondence with power supply voltages to the plurality of delay paths.