Techniques for Phase Detection

Abstract

A phase detection circuit can include two phase detectors that each generate a non-zero output in response to input signals being aligned in phase. The input signals are based on two periodic signals. The phase detection circuit subtracts the output signal of one phase detector from the output signal of the other phase detector to generate a signal having a zero value when the periodic signals are in phase. Alternatively, a phase detector generates a phase comparison signal indicative of a phase difference between periodic signals. The phase comparison signal has a non-zero value in response to input signals to the phase detector being aligned in phase. The input signals are based on the periodic signals. An output circuit receives the phase comparison signal and generates an output having a zero value in response to the periodic signals being aligned in phase.

1 . A circuit comprising:
 a first phase detector generating a first phase comparison signal that is indicative of a phase difference between first and second periodic signals, wherein the first phase comparison signal has a non-zero value in response to first input signals to the first phase detector being aligned in phase, and wherein the first input signals are based on the first and the second periodic signals;   a second phase detector generating a second phase comparison signal that is indicative of a phase difference between the first and the second periodic signals, wherein the second phase comparison signal has a non-zero value in response to second input signals to the second phase detector being aligned in phase, and wherein the second input signals are based on the first and the second periodic signals; and   a combiner circuit that combines the first and the second phase comparison signals to generate a third phase comparison signal having a zero value when the first and the second periodic signals are aligned in phase.   
     
     
         2 . The circuit of  claim 1  further comprising:
 a first delay circuit that delays the second periodic signal to generate a first delayed signal, wherein the first input signals to the first phase detector are the first periodic signal and the first delayed signal; and 
 a second delay circuit that delays the first periodic signal to generate a second delayed signal, wherein the second input signals to the second phase detector are the second periodic signal and the second delayed signal. 
 
     
     
         3 . The circuit of  claim 2  wherein the first delay circuit delays the second periodic signal by approximately 90 degrees to generate the first delayed signal, wherein the second delay circuit delays the first periodic signal by approximately 90 degrees to generate the second delayed signal, and wherein the first and the second phase detectors are quadrature phase detectors. 
     
     
         4 . The circuit of  claim 2  wherein the first and the second phase detectors have substantially the same circuit designs, and wherein the first and the second delay circuits have identical circuit designs. 
     
     
         5 . The circuit of  claim 1  wherein the combiner circuit is a subtraction circuit that subtracts the first phase comparison signal from the second phase comparison signal to generate the third phase comparison signal. 
     
     
         6 . The circuit of  claim 1  wherein the second phase comparison signal is a phase shifted version of the first phase comparison signal when the first and the second phase comparison signals are plotted as a function of a phase difference between the first and the second periodic signals. 
     
     
         7 . The circuit of  claim 1  wherein the first and the second phase detectors are quadrature phase detectors. 
     
     
         8 . The circuit of  claim 1  further comprising:
 a first delay circuit that delays the first periodic signal to generate a first delayed signal; 
 a second delay circuit that delays the second periodic signal to generate a second delayed signal, wherein the first input signals to the first phase detector are the first delayed signal and the second delayed signal; 
 a third delay circuit that delays the first periodic signal to generate a third delayed signal; and 
 a fourth delay circuit that delays the second periodic signal to generate a fourth delayed signal, wherein the second input signals to the second phase detector are the third delayed signal and the fourth delayed signal. 
 
     
     
         9 . The circuit of  claim 8  wherein the first delay circuit delays the first periodic signal by approximately 45 degrees to generate the first delayed signal, wherein the second delay circuit delays the second periodic signal by approximately −45 degrees to generate the second delayed signal, wherein the third delay circuit delays the first periodic signal by approximately −45 degrees to generate the third delayed signal, wherein the fourth delay circuit delays the second periodic signal by approximately 45 degrees to generate the fourth delayed signal, and wherein the first and the second phase detectors are quadrature phase detectors. 
     
     
         10 . The circuit of  claim 8  wherein the first and the second phase detectors have substantially the same circuit designs, wherein the first and the fourth delay circuits have substantially the same circuit designs, and wherein the second and the third delay circuits have substantially the same circuit designs. 
     
     
         11 . The circuit of  claim 1  wherein the first and the second phase detectors are zero phase detectors that have systematic static phase offsets, and wherein the first input signals are the first and the second periodic signals, and the second input signals are the first and the second periodic signals. 
     
     
         12 . The circuit of  claim 11  wherein the first phase detector comprises a first sample and hold circuit that samples the first periodic signal with the second periodic signal, and wherein the second phase detector comprises a second sample and hold circuit that samples the second periodic signal with the first periodic signal. 
     
     
         13 . The circuit of  claim 12  wherein the first sample and hold circuit is coupled to a first low pass filter circuit, wherein the first sample and hold circuit and the first low pass filter circuit generate the first phase comparison signal,
 wherein the second sample and hold circuit is coupled to a second low pass filter circuit, wherein the second sample and hold circuit and the second low pass filter circuit generate the second phase comparison signal, and 
 wherein the combiner circuit is a differencing amplifier that generates the third phase comparison signal based on the first and the second phase comparison signals. 
 
     
     
         14 . The circuit of  claim 12  wherein the first sample and hold circuit comprises a first transistor coupled to a first capacitor, wherein the first periodic signal is received at a channel input of the first transistor, wherein the second periodic signal is received at a control input of the first transistor, wherein the second sample and hold circuit comprises a second transistor coupled to a second capacitor, wherein the second periodic signal is received at a channel input of the second transistor, and wherein the first periodic signal is received at a control input of the second transistor. 
     
     
         15 . The circuit of  claim 1  wherein the circuit is part of a delay-locked loop. 
     
     
         16 . The circuit of  claim 1  wherein the circuit is part of a phase-locked loop. 
     
     
         17 . The circuit of  claim 1  wherein the circuit is embedded in an integrated circuit. 
     
     
         18 . The circuit of  claim 17  wherein the integrated circuit is a memory integrated circuit. 
     
     
         19 . The circuit of  claim 17  wherein the integrated circuit is a memory controller integrated circuit. 
     
     
         20 . A circuit comprising:
 a phase detector generating a phase comparison signal that is indicative of a phase difference between first and second periodic signals, wherein the phase comparison signal has a non-zero value in response to first and second input signals to the phase detector being aligned in phase, and wherein the first and the second input signals are based on the first and the second periodic signals; and   an output circuit receiving the phase comparison signal and generating an output that is indicative of the phase difference between the first and the second periodic signals and that has a zero value in response to the first and the second periodic signals being aligned in phase.   
     
     
         21 . The circuit of  claim 20  further comprising:
 a first chopper switch circuit that periodically switches the first and the second periodic signals to a first output of the first chopper switch circuit, wherein the first chopper switch circuit periodically switches the first and the second periodic signals to a second output of the first chopper switch circuit, and wherein a signal generated at the first output of the first chopper switch circuit is the first input signal to the phase detector; and 
 a delay circuit that delays a signal generated at the second output of the first chopper switch circuit to generate the second input signal to the phase detector. 
 
     
     
         22 . The circuit of  claim 21  further comprising:
 a second chopper switch circuit coupled to an output of the phase detector, 
 wherein the output circuit comprises a load circuit coupled to the second chopper switch circuit, wherein the second chopper switch circuit periodically switches the phase comparison signal and an inverted phase comparison signal generated by the phase detector to an input of the load circuit. 
 
     
     
         23 . The circuit of  claim 22  wherein the phase detector comprises a pull-down network of transistors, and wherein the second chopper switch circuit is coupled between the load circuit and the pull-down network of transistors. 
     
     
         24 . The circuit of  claim 23  wherein the phase detector is an XOR based phase detector. 
     
     
         25 . The circuit of  claim 22  wherein the input of the load circuit is a differential input, and the phase comparison signal is a differential signal. 
     
     
         26 . The circuit of  claim 22  wherein a clock signal controls periodic switching of both the first and the second chopper switch circuits. 
     
     
         27 . The circuit of  claim 20  further comprising:
 a first chopper switch circuit that periodically switches the first and the second periodic signals to a first output of the first chopper switch circuit, and wherein the first chopper switch circuit periodically switches the first and the second periodic signals to a second output of the first chopper switch circuit; and 
 a delay circuit that delays a signal generated at the second output of the first chopper switch circuit to generate the second input signal to the phase detector. 
 
     
     
         28 . The circuit of  claim 20  further comprising:
 a first chopper switch circuit that periodically switches the first and the second periodic signals to a first output of the first chopper switch circuit, and wherein the first chopper switch circuit periodically switches the first and the second periodic signals to a second output of the first chopper switch circuit; 
 a delay circuit that delays a signal generated at the second output of the first chopper switch circuit to generate a delayed signal; and 
 a second chopper switch circuit coupled to the delay circuit and to the first chopper switch circuit, wherein the second chopper switch circuit periodically switches a signal generated at the first output of the first chopper switch circuit and the delayed signal between inputs of the phase detector to generate the first and the second input signals to the phase detector, wherein a clock signal controls periodic switching of both the first and the second chopper switch circuits. 
 
     
     
         29 . The circuit of  claim 21  wherein the phase detector is a quadrature phase detector, and the delay circuit has a delay of approximately 90°. 
     
     
         30 . The circuit of  claim 20  wherein the phase comparison signal is a differential signal. 
     
     
         31 . The circuit of  claim 20  wherein the circuit is part of a delay-locked loop. 
     
     
         32 . The circuit of  claim 20  wherein the circuit is part of a phase-locked loop. 
     
     
         33 . The circuit of  claim 20  wherein the circuit is embedded in an integrated circuit. 
     
     
         34 . A method comprising:
 comparing phases of first and second periodic signals to generate a first phase comparison signal that has a non-zero value in response to first input signals to a first phase detector being in phase, and wherein the first input signals are based on the first and the second periodic signals;   comparing phases of the first and the second periodic signals to generate a second phase comparison signal that has a non-zero value in response to second input signals to a second phase detector being in phase, and wherein the second input signals are based on the first and the second periodic signals; and   combining the first and the second phase comparison signals to generate a phase comparison output that is indicative of a phase difference between the first and the second periodic signals and that has a zero value when the first and the second periodic signals are in phase.   
     
     
         35 . The method of  claim 34  further comprising:
 delaying the second periodic signal to generate a first delayed signal, wherein the first input signals to the first phase detector are the first periodic signal and the first delayed signal; and 
 delaying the first periodic signal to generate a second delayed signal, wherein the second input signals to the second phase detector are the second periodic signal and the second delayed signal. 
 
     
     
         36 . The method of  claim 35  wherein delaying the second periodic signal to generate a first delayed signal further comprises delaying the second periodic signal by approximately 90 degrees to generate the first delayed signal, and wherein delaying the first periodic signal to generate a second delayed signal further comprises delaying the first periodic signal by approximately 90 degrees to generate the second delayed signal. 
     
     
         37 . The method of  claim 34  wherein combining the first and the second phase comparison signals to generate a phase comparison output that is indicative of a phase difference between the first and the second periodic signals and that has a zero value when the first and the second periodic signals are aligned in phase further comprises subtracting the first phase comparison signal from the second phase comparison signal to generate the phase comparison output. 
     
     
         38 . The method of  claim 34  further comprising:
 delaying the first periodic signal to generate a first delayed signal; 
 delaying the second periodic signal to generate a second delayed signal, wherein the first input signals to the first phase detector are the first and the second delayed signals; 
 delaying the first periodic signal to generate a third delayed signal; and 
 delaying the second periodic signal to generate a fourth delayed signal, wherein the second input signals to the second phase detector are the third and the fourth delayed signals. 
 
     
     
         39 . The method of  claim 34  wherein comparing phases of first and second periodic signals to generate a first phase comparison signal further comprises sampling the first periodic signal with the second periodic signal to generate the first phase comparison signal, and wherein comparing phases of the first and the second periodic signals to generate a second phase comparison signal further comprises sampling the second periodic signal with the first periodic signal to generate the second phase comparison signal. 
     
     
         40 . A method comprising:
 comparing phases of first and second periodic signals to generate a phase comparison signal that has a non-zero value in response to first and second input signals to a phase detector being in phase, and wherein the first and the second input signals are based on the first and the second periodic signals; and   generating an output based on the phase comparison signal that is indicative of a phase difference between the first and the second periodic signals and that has a zero value in response to the first and the second periodic signals being in phase.   
     
     
         41 . The method of  claim 40  further comprising:
 periodically switching the first and the second periodic signals to a first output of a first chopper switch circuit and periodically switching the first and the second periodic signals to a second output of the first chopper switch circuit, wherein a signal generated at the first output of the first chopper switch circuit is the first input signal to the phase detector; and 
 delaying a signal generated at the second output of the first chopper switch circuit to generate the second input signal to the phase detector. 
 
     
     
         42 . The method of  claim 41  further comprising:
 alternately and periodically switching the phase comparison signal and an inverted version of the phase comparison signal between inputs of a load circuit using a second chopper switch circuit. 
 
     
     
         43 . The method of  claim 40  further comprising:
 periodically switching the first and the second periodic signals to a first output of a first chopper switch circuit and periodically switching the first and the second periodic signals to a second output of the first chopper switch circuit; and 
 delaying a signal generated at the second output of the first chopper switch circuit to generate a delayed signal. 
 
     
     
         44 . The method of  claim 43  further comprising:
 alternately and periodically switching a signal generated at the first output of the first chopper switch circuit and the delayed signal between outputs of a second chopper switch circuit to generate the first and the second input signals to the phase detector, wherein a clock signal controls periodic switching of both the first and the second chopper switch circuits. 
 
     
     
         45 . The method of  claim 43  further comprising:
 sampling the phase comparison signal to generate first and second sampled signals; and 
 subtracting the first sampled signal from the second sampled signal to generate the output. 
 
     
     
         46 . The method of  claim 41  wherein delaying a signal generated at the second output of the first chopper switch circuit to generate the second input signal to the phase detector further comprises delaying the signal generated at the second output of the first chopper switch circuit by approximately 90° to generate the second input signal to the phase detector.