Strained devices, methods of manufacture and design structures

Abstract

Strained Si and strained SiGe on insulator devices, methods of manufacture and design structures is provided. The method includes growing an SiGe layer on a silicon on insulator wafer. The method further includes patterning the SiGe layer into PFET and NFET regions such that a strain in the SiGe layer in the PFET and NFET regions is relaxed. The method further includes amorphizing by ion implantation at least a portion of an Si layer directly underneath the SiGe layer. The method further includes performing a thermal anneal to recrystallize the Si layer such that a lattice constant is matched to that of the relaxed SiGe, thereby creating a tensile strain on the NFET region. The method further includes removing the SiGe layer from the NFET region. The method further includes performing a Ge process to convert the Si layer in the PFET region into compressively strained SiGe.

1 . A structure, comprising:
 a tensilely strained NFET region comprising an amorphized ion implanted and thermally annealed recrystallized Si layer of a silicon on insulator wafer that has a lattice constant matched to that of a relaxed SiGe layer; and   a compressively strained PFET region comprising an SiGe layer which was converted from a Si layer of the silicon on insulator wafer.   
     
     
         2 . The structure of  claim 1 , wherein the SiGe layer is a grown SiGe on the silicon on insulator wafer. 
     
     
         3 . The structure of  claim 2 , wherein the SiGe layer is a patterned SiGe in the PFET region and the NFET region such that a strain in the SiGe layer in the PFET and NFET regions is relaxed. 
     
     
         4 . The structure of  claim 3 , wherein the amorphized ion implanted and thermally annealed recrystallized Si layer is provided directly underneath the SiGe layer in the NFET region. 
     
     
         5 . The structure of  claim 4 , wherein the lattice constant is matched to that of the relaxed SiGe, thereby creating a tensile strain on the NFET region. 
     
     
         6 . The structure of  claim 1 , wherein parts of the silicon on insulator wafer dedicated for low power NFET and PFET devices are covered with an insulator such that SiGe is not grown on the parts on insulator wafer dedicated for low power NFET and PFET devices. 
     
     
         7 . The structure of  claim 1 , wherein the amorphizing by ion implantation is provided over an entirety of the Si layer and part of the SiGe layer. 
     
     
         8 . A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
 a tensilely strained NFET region comprising an amorphized ion implanted and thermally annealed recrystallized Si layer of a silicon on insulator wafer that has a lattice constant matched to that of a relaxed SiGe layer; and   a compressively strained PFET region comprising an SiGe layer which was converted from a Si layer of the silicon on insulator wafer.   
     
     
         9 . The design structure of  claim 8 , wherein the design structure comprises a netlist. 
     
     
         10 . The design structure of  claim 8 , wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits. 
     
     
         11 . The design structure of  claim 8 , wherein the design structure resides in a programmable gate array.