Method of manufacturing semiconductor chip stack

Abstract

A method of manufacturing a semiconductor chip stack includes providing a circuit layout of a function device, the circuit layout further comprising a first device layout and a second device layout, and an integration density of the first device layout is larger than an integration density of the second device layout; defining a plurality of first chip regions on a first wafer and forming the first device layout in each first chip region; defining a plurality of second chip regions on a second wafer and forming the second device layout in each second chip region; forming a plurality of first TSVs in each first wafer for electrically connecting the first device layout and the second device layout; and respectively cutting the first wafer and the second wafer to form a plurality of first chips and a plurality of second chips.

1 . A method of manufacturing a semiconductor chip stack comprising steps of:
 providing a circuit layout of a function device, the circuit layout further comprising a first device layout and a second device layout, and an integration density of the first device layout is larger than an integration density of the second device layout;   defining a plurality of first chip regions on a first wafer and forming the first device layout in each first chip region;   defining a plurality of second chip regions on a second wafer and forming the second device layout in each second chip region;   forming a plurality of first TSVs in each first wafer for electrically connecting the first device layout and the second device layout; and   respectively cutting the first wafer and the second wafer to form a plurality of first chips and a plurality of second chips.   
     
     
         2 . The method of  claim 1  further comprising a step of forming a plurality of second TSVs in each second chip region. 
     
     
         3 . The method of  claim 1 , wherein the first device layout comprises a core array of a memory. 
     
     
         4 . The method of  claim 3 , wherein the second device layout comprises logic circuits, ESD protection devices and I/O pads of the memory. 
     
     
         5 . The method of  claim 1 , wherein the first device layout comprises at least a core array layout of a first memory and a core array layout of a second memory. 
     
     
         6 . The method of  claim 5 , wherein the second device layout comprises logic circuits, ESD protection devices and I/O pads respectively of the first memory and the second memory. 
     
     
         7 . The method of  claim 1  further comprising:
 providing a third wafer having a plurality of third chip regions defined thereon; 
 forming a third device layout respectively in each third chip region, an integration density of the third device layout is larger than an integration density of the second device layout; and 
 cutting the third wafer to form a plurality of third chips. 
 
     
     
         8 . The method of  claim 7  further comprising a step of forming a plurality of third TSVs in each third chip region. 
     
     
         9 . The method of  claim 7 , wherein the first device layout and the third device layout respectively comprises a core array of a first memory and a core array of a third memory, and the first memory is different from the third memory. 
     
     
         10 . The method of  claim 9 , wherein the second device layout comprises logic circuits, ESD protection devices and I/O pads respective of the first memory and the third memory. 
     
     
         11 . The method of  claim 7 , wherein the first device layout and the third device layout comprises same memory core arrays. 
     
     
         12 . The method of  claim 11 , wherein the second device layout comprises logic circuits, ESD protection devices and I/O pads corresponding to the memory core arrays. 
     
     
         13 . The method of  claim 1  further comprises a step of stacking the first chip and the second chip on a carrier.