Processor power consumption control and voltage drop via micro-architectural bandwidth throttling

Abstract

A method, device, and system are disclosed. In one embodiment the method includes supplying a processor with a first voltage. The method also includes allowing the processor to function within an enhanced processor halt state at the first voltage. The first voltage is a voltage below the lowest compatible voltage for the enhanced processor halt state. The method allows the processor to execute instructions upon waking from the enhanced processor halt state at the first voltage by throttling a maximum throughput rate of instructions being executed in the processor.

1 . A processor, comprising:
 power management logic to enable the processor to perform instructions at a substantially maximum throughput rate after transitioning from a low power state to a higher power state, wherein the processor is to operate at a substantially minimum operating voltage during a time, in which the processor is in the low power state and at a higher operating voltage during a time, in which the processor is in the higher power state.