Semiconductor device including multiple metal semiconductor alloy region and a gate structure covered by a continuous encapsulating layer

Abstract

A method of forming a semiconductor device is provided that in some embodiments encapsulates a gate silicide in a continuous encapsulating material. By encapsulating the gate silicide in the encapsulating material, the present disclosure substantially eliminates shorting between the gate structure and the interconnects to the source and drain regions of the semiconductor device.

1 . A method of forming a semiconductor device comprising:
 forming a gate structure on a semiconductor substrate, the gate structure including a semiconductor containing gate conductor, wherein a source region and a drain region having a surface of a first metal semiconductor alloy are present in the semiconductor substrate on opposing sides of the gate structure and a spacer is adjacent to sidewalls of the gates structure;   forming a first interlevel dielectric layer over the surface of the first metal semiconductor alloy, wherein the first interlevel dielectric layer has an upper surface that is coplanar with the upper surface of the gate structure;   converting the semiconductor containing gate conductor to a second metal semiconductor alloy;   removing the first interlevel dielectric layer;   forming a continuous encapsulating layer over the surface of the first metal semiconductor alloy, the spacer and the gate structure;   forming a second interlevel dielectric layer on the continuous encapsulating layer; and   forming interconnects to the surface of the first metal semiconductor alloy on the source region and the drain region.   
     
     
         2 . The method of  claim 1 , wherein the forming of the interconnects comprises etching a via opening through the second interlevel dielectric layer selective to the continuous encapsulating layer, extending the via opening through the continuous encapsulating layer to an exposed portion of the first metal semiconductor alloy, and forming the interconnect in the via opening in direct contact with the exposed portion of the first metal semiconductor alloy. 
     
     
         3 . The method of  claim 1 , wherein the forming of the gate structure on the semiconductor substrate comprises:
 depositing a gate dielectric layer directly on the semiconductor substrate;   depositing a metal gate conductor layer directly on the gate conductor layer;   depositing a semiconductor containing gate conductor layer directly on the metal gate conductor layer;   depositing a capping dielectric layer directly on the semiconductor containing gate conductor layer;   forming an etch mask overlying the semiconductor containing gate conductor layer; and   etching the capping dielectric layer, the semiconductor containing gate conductor layer, the metal gate conductor layer, and the gate dielectric layer selectively to the etch mask and the semiconductor substrate to provide the gate structure, wherein a first dielectric cap is present on an upper surface of the gate structure.   
     
     
         4 . The method of  claim 3 , wherein the spacer is formed in direct contact with the sidewalls of the gate structure, and the source region and the drain region are formed in the semiconductor substrate by ion implantation. 
     
     
         5 . The method of  claim 4 , wherein the first metal semiconductor alloy is formed by depositing a first metal layer on the surface of the source region and the drain region; annealing to intermix the first metal layer and a semiconductor from the semiconductor substrate in the source region and the drain region; and removing non-reacted portions of the first metal layer. 
     
     
         6 . The method of  claim 1 , wherein the forming of the first interlevel dielectric layer over the surface of the first metal semiconductor alloy comprises:
 depositing the first interlevel dielectric layer over the gate structure, the spacer and the surface of the first metal semiconductor alloy; and   planarizing the first interlevel dielectric layer until the upper surface is coplanar with an upper surface of a remaining portion of the first interlevel dielectric layer.   
     
     
         7 . The method of  claim 2 , wherein the gate stack further includes a first dielectric cap, and the converting of the semiconductor containing gate conductor to a second metal semiconductor alloy comprises:
 removing the first dielectric cap with an etch that is selective to the semiconductor containing gate conductor;   depositing a second metal layer on at least an exposed surface of the semiconductor containing gate conductor;   annealing to intermix the second metal layer and the semiconductor containing gate conductor;   removing non-reacted portions of the second metal layer; and   forming a second dielectric cap on the second metal conductor alloy having an upper surface that is coplanar with the upper surface of the first interlevel dielectric layer.   
     
     
         8 . The method of  claim 1 , wherein the forming of the continuous encapsulating layer over the surface of the first metal semiconductor alloy comprises depositing a single dielectric material layer over the surface of the first metal semiconductor alloy, the spacer, and the second metal semiconductor alloy of the gate structure. 
     
     
         9 . The method of  claim 7  further comprising forming a conformal dielectric layer on the gate structure, the spacer and the surface of the first metal semiconductor alloy before forming the first interlevel dielectric layer, and removing a portion of the conformal dielectric layer from the upper surface of the gate structure when the first interlevel dielectric layer is planarized so that the first interlevel dielectric layer has an upper surface that is coplanar with the upper surface of the gate structure, wherein a remaining portion of the conformal dielectric layer is present in direct contact with the spacer and the surface of the first metal semiconductor alloy. 
     
     
         10 . The method of  claim 9 , wherein the forming of the continuous encapsulating layer over the surface of the first metal semiconductor alloy comprises depositing a single dielectric material layer in direct contact with the conformal dielectric layer that is in direct contact with the first metal semiconductor alloy and the spacer, and in direct contact with the second dielectric cap that is in direct contact with the second metal conductor alloy. 
     
     
         11 . The method of  claim 1 , wherein the forming of the second interlevel dielectric layer on the continuous encapsulating layer comprises forming the second interlevel dielectric layer in direct contact with the continuous encapsulating layer that is over the surface of the first metal semiconductor alloy, the spacer, and the second metal semiconductor alloy of the gate structure. 
     
     
         12 . The method of  claim 10 , wherein the extending of the via opening through the continuous encapsulating layer to an exposed portion of the first metal semiconductor alloy comprises:
 etching the continuous encapsulating layer selective to the conformal dielectric layer; and   etching the conformal dielectric layer selective to the first metal semiconductor alloy.   
     
     
         13 . The method of  claim 2 , wherein the forming of the interconnect in the via opening in direct contact with the exposed portion of the first metal semiconductor alloy comprises depositing a metal into the via opening using physical vapor deposition (PVD). 
     
     
         14 . A method of forming a semiconductor device comprising:
 forming a gate structure on a semiconductor substrate including a semiconductor containing gate conductor, wherein a source region and a drain region having a surface of a first metal semiconductor alloy are present in the semiconductor substrate on opposing sides of the gate structure;   forming a conformal dielectric layer over the gate structure and the surface of the first metal semiconductor alloy;   forming a first interlevel dielectric layer over the conformal dielectric layer;   planarizing to expose an upper surface of the gate structure, wherein the remaining portion of the conformal dielectric layer and the first interlevel dielectric layer have an upper surface substantially coplanar with the upper surface of the gate structure;   converting the semiconductor containing gate conductor of the gate structure to a second metal semiconductor alloy;   removing the first interlevel dielectric layer;   forming a continuous encapsulating layer in direct contact with the remaining portion of the conformal dielectric and over the second metal semiconductor alloy of the gate structure;   forming a second interlevel dielectric layer on the continuous encapsulating layer; and   forming interconnects to the surface of the first metal semiconductor alloy on the source region and the drain region.   
     
     
         15 . The method of  claim 14 , wherein the forming of the interconnects comprises etching a via opening through the second interlevel dielectric layer selective to the continuous encapsulating layer, extending the via opening through the continuous encapsulating layer to an exposed portion of the first metal semiconductor alloy, and forming the interconnect in the via opening in direct contact with the exposed portion of the first metal semiconductor alloy. 
     
     
         16 . The method of  claim 14 , wherein the gate structure further includes a first dielectric cap, and the converting of the semiconductor containing gate conductor to a second metal semiconductor alloy comprises:
 removing the first dielectric cap with an etch that is selective to the semiconductor containing gate conductor;   depositing a metal layer on at least an exposed surface of the semiconductor containing gate conductor;   annealing to intermix the metal layer and the semiconductor containing gate conductor;   removing non-reacted portions of the metal layer; and   forming a second dielectric cap on the second metal conductor alloy having an upper surface that is coplanar with the upper surface of the first interlevel dielectric layer.   
     
     
         17 . A semiconductor device comprising:
 a gate structure on a channel region of a semiconductor substrate, wherein the gate structure includes a gate dielectric on the semiconductor substrate, a metal gate conductor on the gate dielectric and a metal semiconductor alloy gate conductor on the metal gate conductor;   at least one spacer present on the sidewalls of the gate structure;   a source region and a drain region present in contact with the semiconductor substrate on opposing sides of the channel region, wherein each of the source region and the drain region include a metal semiconductor contact having a different composition than the metal semiconductor alloy gate conductor;   and   a continuous encapsulating dielectric layer extending over the gate structure, the at least one spacer and at least a portion of the source and drain region.   
     
     
         18 . The semiconductor device of  claim 17 , further comprising a uniform dielectric layer between the continuous encapsulating dielectric layer, the at least one spacer and the metal semiconductor contact. 
     
     
         19 . The semiconductor device of  claim 17 , wherein the metal semiconductor alloy gate conductor is comprised of cobalt silicide (CoSi 2 ), and the metal semiconductor contact is comprised of nickel silicide. 
     
     
         20 . The semiconductor device of  claim 17 , wherein the continuous encapsulating dielectric layer is composed of a high-k dielectric.