Low power memory control circuits and methods

Abstract

Circuits and methods for suppressing integrated circuit leakage currents are described. Many of these circuits and methods are particularly well-suited for use in dynamic memory circuits. Examples describe the use of power, ground, or both and power and ground source transistors used for generating virtual voltages. An aspect of the invention describes lowering refresh current. An aspect describes reducing the standby current. An aspect of the invention describes lowering leakage resulting from duplicated circuits, such as row decoders and word line drivers. An aspect describes methods of performing early wake-up of source transistors. A number of source transistor control mechanisms are taught. Circuit layouts methods are taught for optimizing integrated circuit layouts using the source transistors.

1 - 49 . (canceled) 
     
     
         50 . A dynamic memory (DRAM) device, comprising:
 a plurality of memory cells;   a pair of bitlines coupled to said memory cells;   said memory cells are configured to maintain memory state in response to performing refresh operations; and   said memory cells are configured with a cell data high potential which is boosted in self-refresh, or system controlled, refresh mode.   
     
     
         51 . A dynamic memory as recited in  claim 50 , wherein the equalized bitline voltage level is higher in self-refresh mode than in normal operating mode. 
     
     
         52 . A dynamic memory as recited in  claim 51 , wherein the higher equalized bitline level in self-refresh mode is controlled by a bitline precharge level generator. 
     
     
         53 . A dynamic memory as recited in  claim 50 , wherein the equalized bitline voltage level is higher than the output level of a precharge level generator for a bitline. 
     
     
         54 . A dynamic memory as recited in  claim 50 , wherein the boosted voltage potential is controlled by a reference voltage signal through an error detector, a pulse signal, a combination of existing signal, or a combination of reference voltage signal, pulse signal and mode entry and/or exit signals. 
     
     
         55 . A dynamic memory as recited in  claim 50 , wherein the source transistor generating cell data high potential comprises at least a first, second and third source transistor. 
     
     
         56 . A dynamic memory as recited in  claim 55 , wherein said first source transistor comprises a PMOS source transistor, and said second and third source transistors comprise NMOS source transistors. 
     
     
         57 . A dynamic memory as recited in  claim 56 , wherein said first transistor is configured for speeding up supply power. 
     
     
         58 . A dynamic memory as recited in  claim 57 , wherein said first source transistor is connected to a power supply that is higher than the supply voltage of second and third source transistors. 
     
     
         59 . A dynamic memory as recited in  claim 56 , wherein said second source transistor generates main power. 
     
     
         60 . A dynamic memory as recited in  claim 56 , wherein said third source transistor generates auxiliary power. 
     
     
         61 . A dynamic memory as recited in  claim 56 , wherein the source of first PMOS source transistor and the drain of first NMOS source transistor is connected to internally generated power and the drain of second NMOS source transistor is connected to externally supplied power. 
     
     
         62 . A dynamic memory as recited in  claim 61 , wherein the gate of second NMOS source transistor is controlled by a pulse or a combination of pulse and mode entry and/or exit signals. 
     
     
         63 . A dynamic memory as recited in  claim 62 , wherein the second NMOS source transistor is configured to provide a turn-on time in self-refresh mode that exceeds the turn-on time in normal operating mode. 
     
     
         64 . A dynamic memory (DRAM) device, comprising:
 a plurality of memory cells whose memory state is maintained in response to performing refresh operations;   a pair of bitlines coupled to said memory cells;   a bitline sense amplifier coupled to said bitlines for sensing the state of said memory cells;   a plurality of source transistors coupled to said bitline sense amplifier;   said plurality of source transistors comprises a first PMOS source transistor, a first NMOS source transistor, and a second NMOS source transistor; and   said source transistors are connected to a latch within said bitline sense amplifier.   
     
     
         65 . A dynamic memory as recited in  claim 64 , wherein:
 the source of said first PMOS source transistor, and the drain of first NMOS source transistor, are connected to internally generated power; and   the drain of said second NMOS source transistor is connected to externally supplied power.   
     
     
         66 . A dynamic memory as recited in  claim 64 , wherein the gate of said second NMOS source transistor is controlled by a pulse, or a combination of pulse and mode entry and/or exit signal 
     
     
         67 . A dynamic memory (DRAM) device, comprising:
 a plurality of memory cells;   wherein memory state of said dynamic memory is maintained in response to performing refresh operations;   a pair of bitlines coupled to said memory cells;   a bitline sense amplifier coupled to said bitlines for sensing the state of said memory cells; and   a plurality of source transistors coupled to said bitline sense amplifier and configured to increase the voltage potential of memory cell high data.   
     
     
         68 . A dynamic memory as recited in  claim 67 , wherein said plurality of source transistors comprises three source transistors. 
     
     
         69 . A dynamic memory as recited in  claim 68 , wherein:
 said plurality of source transistors comprises a first PMOS source transistor, a first NMOS source transistor, and a second NMOS source transistor; and   said source transistors are connected to a latch within said bitline sense amplifier.   
     
     
         70 . A dynamic memory as recited in  claim 68 , wherein:
 a first of said plurality of source transistors is used to speed up supply power by being connected to a power supply configured with a higher voltage potential than the supply voltage of a second source transistor and a third source transistor within said plurality of source transistors;   said second source transistor is configured to deliver main power; and   said third source transistor is configured to deliver auxiliary power.   
     
     
         71 - 131 . (canceled)