Method of fabrication of metal oxide semiconductor field effect transistor

Abstract

A method of fabrication of a metal oxide semiconductor field effect transistor includes first providing a substrate on which a gate structure is formed. Afterwards, a portion of the substrate is removed to form a first recess in the substrate at both ends of the gate structure. Additionally, a source/drain extension layer is deposited in the first recess and a number of spacers are formed at both ends of the gate structure. Subsequently, a portion of the source/drain extension and the substrate are removed to form a second recess in the source/drain extension and a portion of the substrate outside of the spacer. In addition, a source/drain layer is deposited in the second recess. Because the source/drain extension and the source/drain layer have specific materials and structures, short channel effect is improved and the efficiency of the metal oxide semiconductor field effect transistor is improved.

1 . A metal oxide semiconductor field effect transistor, comprising:
 a substrate;   a gate structure, disposed on the substrate;   a spacer, disposed on a side wall of the gate structure;   a source/drain extension layer, disposed in the substrate and below the spacer;
 a source/drain layer, disposed in the substrate and outside of the spacer, wherein the depth of the source/drain layer is larger than the depth of the source/drain extension layer; and 
 a dopant diffusion barrier layer, disposed directly under the source/drain extension layer and in a side of the source/drain extension layer near the gate structure; 
 wherein an entire of the source/drain layer is comprised of a strained material comprising two different atoms. 
   
     
     
         2 . The metal oxide semiconductor field effect transistor of  claim 1 , wherein the strained material is silicon germanium. 
     
     
         3 . The metal oxide semiconductor field effect transistor of  claim 1 , wherein the source/drain extension layer is comprised of the strained material. 
     
     
         4 . The metal oxide semiconductor field effect transistor of  claim 3 , wherein the dopant diffusion barrier layer is comprised of the strained material. 
     
     
         5 . The metal oxide semiconductor field effect transistor of  claim 1 , wherein the strained material is silicon carbide. 
     
     
         6 . A metal oxide semiconductor field effect transistor, comprising:
 a substrate;   a gate structure, disposed on the substrate;   a spacer, disposed on a side wall of the gate structure;   a source/drain extension layer, disposed in the substrate and below the spacer;   a source/drain layer, disposed in the substrate and outside of the spacer, wherein the depth of the source/drain layer is larger than the depth of the source/drain extension layer; and   a dopant diffusion barrier layer, disposed directly under the source/drain extension layer;   wherein an entire of the source/drain extension layer and the dopant diffusion barrier layer are comprised of a strained material comprising two different atoms.   
     
     
         7 . The metal oxide semiconductor field effect transistor of  claim 6 , wherein the source/drain extension layer and the dopant diffusion barrier layer are located between an edge of the gate structure and an edge of the source/drain layer. 
     
     
         8 . The metal oxide semiconductor field effect transistor of  claim 6 , wherein the dopant diffusion barrier layer is further disposed directly in a side of the source/drain extension layer near the gate structure. 
     
     
         9 . The metal oxide semiconductor field effect transistor of  claim 8 , wherein a gap is disposed between the source/drain extension layer, the dopant diffusion barrier layer and the edge of the gate structure. 
     
     
         10 . The metal oxide semiconductor field effect transistor of  claim 6 , wherein the source/drain extension layer and the dopant diffusion barrier layer are of different conductivity types. 
     
     
         11 . A metal oxide semiconductor field effect transistor, comprising:
 a substrate;   a gate structure, disposed on the substrate;   a spacer, disposed on a side wall of the gate structure;   a source/drain extension layer, disposed in the substrate and below the spacer;   a source/drain layer, disposed in the substrate and outside of the spacer, wherein the depth of the source /drain layer is larger than the depth of the source/drain extension layer; and   a dopant diffusion barrier layer, disposed directly under the source/drain extension layer;   wherein a top surface of the source/drain extension layer is higher than a top surface of the substrate.   
     
     
         12 . The metal oxide semiconductor field effect transistor of  claim 11 , wherein a top surface of the source/drain layer is higher than the top surface of the source/drain extension layer. 
     
     
         13 . The metal oxide semiconductor field effect transistor of  claim 11 , wherein an entire of the source/drain extension layer is comprised of a strained material comprising two different atoms. 
     
     
         14 . The metal oxide semiconductor field effect transistor of  claim 11 , wherein the strained material is silicon germanium. 
     
     
         15 . The metal oxide semiconductor field effect transistor of  claim 14 , wherein the germanium composition ratio of the source/drain extension layer is of gradient distribution. 
     
     
         16 . The metal oxide semiconductor field effect transistor of  claim 15 , wherein the germanium composition ratio of the portion of the source/drain extension layer adjacent to the substrate is larger than the germanium composition ratio of the portion of the source/drain extension layer disposed at a farther distance to the substrate.