Selectable jtag or trace access with data store and output

Abstract

An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

1 . An integrated circuit comprising:
 A. an address and command port having a data input and output lead, a clock lead, a trace output lead, a run/test idle lead, a ShiftDR lead, a trace clock lead, a trace data out lead, a test data in lead, a test mode select lead, a test clock lead, and a test data out lead;   B. trace circuitry having a trace input connected to the trace output lead, a run/test idle input connected to the run/test idle lead, a ShiftDR input connected to the ShiftDR lead, a trace clock input connected to the trace clock lead, and a trace data input connected to the trace data out lead; and   C. TAP domain circuitry having a test data input connected to the test data in lead, a test mode select input connected to the test mode select lead, a test clock input connected to the test clock lead, and a test data output connected to the test data out lead.   
     
     
         2 . The integrated circuit of  claim 1  in which the address and command port includes serial input parallel output circuitry having a serial input coupled to the data input and output lead and, a test mode select output, a test data output, and a clock input coupled to the clock lead. 
     
     
         3 . The integrated circuit of  claim 1  in which the address and command port includes serial input parallel output circuitry having a serial input coupled to the data input and output lead and, a test mode select output, a test data output, and a clock input coupled to the clock lead, the address and command port including a register having inputs connected to the outputs of the serial input parallel output circuitry and having a select mode output coupled to the test mode select lead, and a test in data output coupled to the test data in lead.