Power MOSFET Having a Strained Channel in a Semiconductor Heterostructure on Metal Substrate

Abstract

A method for forming a semiconductor device includes forming a graded silicon-germanium (SiGe) layer overlying a silicon substrate, a concentration of germanium increasing with a thickness of the graded silicon germanium layer. A first relaxed SiGe layer is formed over the graded SiGe layer, and a second relaxed SiGe layer overlying the first relaxed SiGe layer. The second relaxed SiGe layer has a lower conductivity than the first relaxed SiGe layer. The method also includes forming a field effect transistor having a trench extending into the second relaxed SiGe layer and a channel region that includes a layer of strained silicon to enable enhanced carrier mobility. A top conductor layer is formed overlying the second relaxed SiGe layer, and then the silicon substrate and the graded SiGe layer are removed. A bottom conductor layer is formed underlying the first relaxed SiGe layer.

1 . A method for forming a semiconductor device, the method comprising:
 forming a graded SiGe (silicon-germanium) layer overlying a silicon substrate, a concentration of germanium increasing with a thickness of the graded SiGe layer;   forming a first relaxed SiGe layer over the graded SiGe layer;   forming a second relaxed SiGe layer overlying the first relaxed SiGe layer, the second relaxed SiGe layer having a lower conductivity than the first relaxed SiGe layer;   forming a field effect transistor having a trench extending into the second relaxed SiGe layer and a channel region that includes a layer of strained silicon to enable an enhanced carrier mobility;   forming a top conductor layer overlying the second relaxed SiGe layer;   removing the silicon substrate and the graded SiGe layer to expose a backside of the first relaxed SiGe layer; and   forming a bottom conductor layer in direct contact with the first relaxed SiGe layer.   
     
     
         2 . The method of  claim 1  wherein each of the first and the second relaxed SiGe layers comprises 20-30% of germanium. 
     
     
         3 . The method of  claim 1  wherein removing the silicon substrate and the graded SiGe layer comprises:
 bonding a support substrate to the top conductor layer; 
 removing the silicon substrate to expose a back surface of graded SiGe layer; 
 removing at least a portion of the graded SiGe layer using an etch process that has an etch rate dependent on a composition of the graded SiGe layer, wherein the etch process substantially stops at a predetermined concentration of germanium in the graded SiGe layer; and 
 removing the rest of the graded SiGe layer to expose a back surface of the first relaxed SiGe layer before forming the bottom conductor layer. 
 
     
     
         4 . The method of  claim 3  wherein removing at least a portion of the graded SiGe layer comprises using a wet etching process including tetramethylammonium hydroxide (TMAH). 
     
     
         5 . The method of  claim 3  wherein removing the silicon substrate comprises removing the silicon substrate using a wet etching process including potassium hydroxide (KOH) or ethylenediamine pyrocatechol (EDP). 
     
     
         6 . The method of  claim 1  wherein the bottom conductor layer has sufficient thickness for supporting the semiconductor device. 
     
     
         7 . A method for forming a semiconductor device, the method comprising:
 providing a semiconductor substrate including a first semiconductor material;   forming a layer of graded heterostructure overlying the semiconductor substrate, the layer of graded heterostructure including the first semiconductor material and a second semiconductor material, a concentration of the second semiconductor material increasing with a thickness of the graded heterostructure;   forming a first relaxed heterostructure overlying the layer of graded heterostructure, the first relaxed heterostructure including the first semiconductor material and the second semiconductor material, the first relaxed heterostructure being heavily doped and characterized by a first conductivity;   forming a second relaxed heterostructure overlying the first relaxed heterostructure, the second relaxed heterostructure including the first semiconductor material and the second semiconductor material, the second relaxed heterostructure having a second conductivity that is lower than the first conductivity;   forming a field effect transistor having a trench extending into the second relaxed heterostructure and a channel region that includes a layer of strained first semiconductor material lining a sidewall of the trench;   forming a top conductor layer overlying the second relaxed heterostructure;   removing the semiconductor substrate and the layer of graded heterostructure to expose a backside of the first relaxed heterostructure; and   forming a bottom conductor layer underlying the heavily doped first relaxed heterostructure;   wherein a current conduction in the channel region is characterized by an enhanced carrier mobility in the layer of strained first semiconductor material.   
     
     
         8 . The method of  claim 7  wherein removing the semiconductor substrate and the layer of graded heterostructure comprises:
 bonding a support substrate to the top conductor layer; 
 removing the semiconductor substrate to expose a back surface of the layer of graded heterostructure; 
 removing at least a portion of the graded heterostructure using an etch process that has an etch rate dependent on a composition of the graded heterostructure, wherein the etch process substantially stops at a predetermined concentration of the second semiconductor material in the graded heterostructure; and 
 removing the rest of the graded heterostructure to expose a back surface of the first relaxed heterostructure before forming the bottom conductor layer. 
 
     
     
         9 . The method of  claim 7  wherein each of the first and the second relaxed heterostructures comprises a relaxed SiGe heterostructure and the channel region comprises a strained silicon layer. 
     
     
         10 . The method of  claim 9  wherein each of the first and the second relaxed heterostructures comprises 20-30% of germanium. 
     
     
         11 . The method of  claim 9  wherein removing at least a portion of the graded heterostructure comprises using a wet etching process including tetramethylammonium hydroxide (TMAH). 
     
     
         12 . The method of  claim 9  wherein removing the semiconductor substrate comprises removing the semiconductor substrate using a wet etching process including potassium hydroxide (KOH) or ethylenediamine pyrocatechol (EDP). 
     
     
         13 . The method of  claim 7  wherein the first relaxed heterostructure layer has a thickness between approximately 0.5 μm to approximately 3 μm. 
     
     
         14 . The method of  claim 7  wherein the first relaxed heterostructure is characterized by a doping concentration of 1.0×10 19  cm −3  or higher. 
     
     
         15 . The method of  claim 7  wherein each of the first and the second relaxed heterostructures is an epitaxial layer. 
     
     
         16 . The method of  claim 7  wherein the bottom conductor layer has a thickness of about 30-100 μm. 
     
     
         17 . The method of  claim 7  wherein the field effect transistor comprises a trench gate MOSFET, wherein forming the field effect transistor comprising:
 forming a body region in an upper portion of the second relaxed heterostructure, a lower portion of the second relaxed heterostructure being configured to function as a drift region; 
 forming a trench extending into the second relaxed heterostructure; 
 forming a channel region that includes a layer of strained first semiconductor material lining a sidewall of the trench; 
 forming a gate dielectric layer having a high dielectric constant material lining a trench sidewall; 
 forming a gate electrode over the gate dielectric in the trench; and 
 forming source regions flanking each side of the gate electrode in the trench. 
 
     
     
         18 . The method of  claim 17  wherein the second relaxed heterostructure is n-type and the trench gate MOSFET is a p-type MOSFET, wherein the source regions are p-type, the body region is n-type, the drift region is p-type, and the drain region is p-type. 
     
     
         19 . The method of  claim 17  wherein the second relaxed heterostructure is p-type and the trench gate MOSFET is an n-type MOSFET, wherein the source regions are n-type, the body region is p-type, the drift region is n-type, and the drain region is n-type. 
     
     
         20 . The method of  claim 17  wherein the field effect transistor comprises a shielded gate trench MOSFET wherein forming the field effect transistor further comprises:
 forming a shield dielectric lining sidewalls and a bottom surface of each of the trenches; 
 forming a shield electrode in a lower portion of the trench, the shield electrode being insulated from the trench surface by the shield dielectric; and 
 forming an inter-electrode dielectric overlying the shield electrode.