Logic circuit and method of logic circuit design

Abstract

A complementary logic circuit contains first and second logic inputs, first and second dedicated logic terminals, a high-voltage terminal configured for connection to a high constant voltage, a low-voltage terminal configured for connection to a low constant voltage, a p-type transistor and an n-type transistor. The p-type transistor and n-type transistor each have a respective outer diffusion connection, gate connection, inner diffusion connection, and bulk connection. The first and second dedicated logic terminals are connected respectively to the outer diffusion connection of the p-type transistor and the outer diffusion connection of the n-type transistor. The inner diffusion connection of the p-type transistor and the inner diffusion connection of the n-type transistor are connected together to form a common diffusion logic terminal. The high-voltage terminal and the low-voltage terminal are connected respectively to the bulk connection of the p-type transistor and the bulk connection of the n-type transistor.

1 . A complementary logic cell, comprising:
 a first logic input;   a second logic input;   a first dedicated logic terminal;   a second dedicated logic terminal;   a high-voltage terminal configured for connection to a high constant voltage;   a low-voltage terminal configured for connection to a low constant voltage;   a p-type transistor, having an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection; and   an n-type transistor, having an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection;   said first dedicated logic terminal being connected to said outer diffusion connection of said p-type transistor, said second dedicated logic terminal being connected to said outer diffusion connection of said n-type transistor, said inner diffusion connection of said p-type transistor and said inner diffusion connection of said n-type transistor being connected to form a common diffusion logic terminal, said high-voltage terminal being connected to said bulk connection of said p-type transistor, and said low-voltage terminal being connected to said bulk connection of said n-type transistor.   
     
     
         2 . A complementary logic circuit according to  claim 1 , wherein said first and second logic inputs are connected to form a first common logic input. 
     
     
         3 . A complementary logic circuit, comprising:
 a first logic input;   a second logic input;   a first dedicated logic terminal;   a second dedicated logic terminal;   a high-voltage terminal configured for connection to a high constant voltage;   a low-voltage terminal configured for connection to a low constant voltage;   a first logic block comprising:
 a network of p-type transistors for implementing a predetermined logic function, said network having an outer diffusion connection, a first network gate connection, an inner diffusion connection, and a bulk connection, 
 said outer diffusion connection of said p-type transistor network being connected to said first dedicated logic terminal, said first network gate connection of said p-type transistor network being connected to said first logic input, and said bulk connection of said p-type transistor network being connected to said high-voltage terminal; and 
   a second logic block comprising:
 a network of n-type transistors implementing logic function complementary to said predetermined logic function, said network having an outer diffusion connection, a first network gate connection, an inner diffusion connection, and a bulk connection, 
 said outer diffusion connection of said n-type transistor network being connected to said second dedicated logic terminal, said first network gate connection of said n-type transistor network being connected to said second logic input, and said bulk connection of said n-type transistor network being connected to said low-voltage terminal; 
   said inner diffusion connections of said p-type network and of said n-type network being connected to form a common diffusion logic terminal.   
     
     
         4 . A complementary logic circuit according to  claim 3 , wherein said first and second logic inputs are connected to form a first common logic input. 
     
     
         5 . A complementary logic circuit according to  claim 3 , wherein each of said logic terminals is separately configurable to serve as a logic input. 
     
     
         6 . A complementary logic circuit according to  claim 3 , wherein each of said logic terminals is separately configurable to serve as a logic output. 
     
     
         7 . A complementary logic circuit according to  claim 3 , further comprising a third logic input connected to a second network gate connection of said p-type transistor network. 
     
     
         8 . A complementary logic circuit according to  claim 3 , further comprising a fourth logic input connected to a second network gate connection of said n-type transistor network. 
     
     
         9 . A complementary logic circuit according to  claim 7 , further comprising a fourth logic input connected to a second network gate connection of said n-type transistor network. 
     
     
         10 . A complementary logic circuit according to  claim 9 , said third and fourth logic inputs being connected to form a second common logic input. 
     
     
         11 . A complementary logic circuit according to  claim 3 , wherein said p-type transistor network comprises a single p-type transistor. 
     
     
         12 . A complementary logic circuit according to  claim 3 , wherein said n-type transistor network comprises a single n-type transistor. 
     
     
         13 . A complementary logic circuit according to  claim 3 , wherein said network of p-type transistors comprises one of a group of networks comprising: a network of p-type field effect transistors (FET), a network of p-type p-well complementary metal-oxide semiconductor (CMOS) transistors, a network of p-type n-well complementary metal-oxide semiconductor (CMOS) transistors, a network of p-type twin-well complementary metal-oxide semiconductor (CMOS) transistors, a network of p-type silicon on insulator (SOI) transistors, and a network of p-type silicon on sapphire (SOS) transistors. 
     
     
         14 . A complementary logic circuit according to  claim 3 , wherein said network of n-type transistors comprises one of a group of networks comprising: a network of n-type FETs, a network of n-type p-well CMOS transistors, a network of n-type n-well CMOS transistors, a network of n-type twin-well CMOS transistors, a network of n-type SOI transistors, and a network of n-type SOS transistors. 
     
     
         15 . A logic circuit, comprising interconnected logic elements, said logic elements comprising:
 a first logic input;   a second logic input;   a first dedicated logic terminal;   a second dedicated logic terminal;   a high-voltage terminal configured for connection to a high constant voltage;   a low-voltage terminal configured for connection to a low constant voltage;   a p-type transistor, having an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection; and   an n-type transistor, having an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection;   said first logic input being connected to said gate connection of said p-type transistor, said second logic input being connected to said gate connection of said n-type transistor, said first dedicated logic terminal being connected to said outer diffusion connection of said p-type transistor, said second dedicated logic terminal being connected to said outer diffusion connection of said n-type transistor, said inner diffusion connection of said p-type transistor and said inner diffusion connection of said n-type transistor being connected to form a common diffusion logic terminal, said high-voltage terminal being connected to said bulk connection of said p-type transistor, and said low-voltage terminal being connected to said bulk connection of said n-type transistor.   
     
     
         16 . A logic circuit according to  claim 15 , wherein for each of logic elements said first and second logic inputs are connected to form a common logic input. 
     
     
         17 . A logic circuit according to  claim 15 , wherein for each of logic elements each of said logic terminals is separately configurable to serve as a logic input. 
     
     
         18 . A logic circuit according to  claim 15 , wherein for each of logic elements each of said logic terminals is separately configurable to serve as a logic output. 
     
     
         19 . A logic circuit according to  claim 15 , wherein a type of said p-type transistors comprises one of a group of transistor types comprising: p-type FET transistors, p-type p-well CMOS transistors, p-type n-well CMOS transistors, p-type twin-well CMOS transistors, p-type SOI transistors, and p-type SOS transistors. 
     
     
         20 . A logic circuit according to  claim 15 , wherein said a type of n-type transistors comprises one of a group of transistor types comprising: n-type FET transistors, n-type p-well CMOS transistors, n-type n-well CMOS transistors, n-type twin-well CMOS transistors, n-type SOI transistors, and n-type SOS transistors. 
     
     
         21 . A logic circuit, comprising interconnected logic elements, said logic elements comprising:
 a first logic input;   a second logic input;   a first dedicated logic terminal;   a second dedicated logic terminal;   a high-voltage terminal configured for connection to a high constant voltage;   a low-voltage terminal configured for connection to a low constant voltage;   a first logic block comprising:
 a network of p-type transistors for implementing a predetermined logic function, said network having an outer diffusion connection, a first network gate connection, an inner diffusion connection, and a bulk connection, 
 said outer diffusion connection of said p-type transistor network being connected to said first dedicated logic terminal, said first network gate connection of said p-type transistor network being connected to said first logic input, and said bulk connection of said p-type transistor network being connected to said high-voltage terminal; and 
   a second logic block comprising:
 a network of n-type transistors implementing logic function complementary to said predetermined logic function, said network having an outer diffusion connection, a first network gate connection, an inner diffusion connection, and a bulk connection, 
 said outer diffusion connection of said n-type transistor network being connected to said second dedicated logic terminal, said first network gate connection of said n-type transistor network being connected to said second logic input, and said bulk connection of said n-type transistor network being connected to said low-voltage terminal; 
   said inner diffusion connections of said p-type network and of said n-type network being connected to form a common diffusion logic terminal.   
     
     
         22 . A logic circuit according to  claim 21 , wherein for each of said logic elements said first and second logic inputs are connected to form a first common logic input. 
     
     
         23 . A logic circuit according to  claim 21 , wherein for each of said logic elements each of said logic terminals is separately configurable to serve as a logic input. 
     
     
         24 . A logic circuit according to  claim 21 , wherein for each of said logic elements each of said logic terminals is separately configurable to serve as a logic output. 
     
     
         25 . A logic circuit according to  claim 21 , further comprising a third logic input connected to a second network gate connection of said p-type transistor network. 
     
     
         26 . A logic circuit according to  claim 21 , further comprising a fourth logic input connected to a second network gate connection of said n-type transistor network. 
     
     
         27 . A complementary logic circuit according to  claim 25 , further comprising a fourth logic input connected to a second network gate connection of said n-type transistor network. 
     
     
         28 . A complementary logic circuit according to  claim 27 , said third and fourth logic inputs being connected to form a second common logic input. 
     
     
         29 . A logic circuit according to  claim 21 , wherein said p-type transistor network comprises a single p-type transistor. 
     
     
         30 . A logic circuit according to  claim 21 , wherein said n-type transistor network comprises a single n-type transistor. 
     
     
         31 . A logic circuit according to  claim 21 , wherein said network of p-type transistors comprises one of a group of networks comprising: a network of p-type field effect transistors (FET), a network of p-type p-well complementary metal-oxide semiconductor (CMOS) transistors, a network of p-type n-well complementary metal-oxide semiconductor (CMOS) transistors, a network of p-type twin-well complementary metal-oxide semiconductor (CMOS) transistors, a network of p-type silicon on insulator (SOI) transistors, and a network of p-type silicon on sapphire (SOS) transistors. 
     
     
         32 . A logic circuit according to  claim 21 , wherein said network of n-type transistors comprises one of a group of networks comprising: a network of n-type FETs, a network of n-type p-well CMOS transistors, a network of n-type n-well CMOS transistors, a network of n-type twin-well CMOS transistors, a network of n-type SOI transistors, and a network of n-type SOS transistors.