Wiring structure of semiconductor device and method of manufacturing the wiring structure

Abstract

A wiring structure of a semiconductor device, includes: an insulating layer formed on a base member; a first metal layer covered with the insulating layer; a second metal layer having a plurality of electrode parts which are arranged on the insulating layer to be spaced from each other and which have a thickness larger than the first metal layer, the insulating layer having a plurality of via holes which connect the first metal layer and the plurality of electrode parts; and a plurality of through wiring lines which are located within the plurality of via holes and which electrically connect the plurality of electrode parts to the first metal layer.

1 . A wiring structure of a semiconductor device, comprising:
 an insulating layer formed on a base member;   a first metal layer covered with the insulating layer; and   a second metal layer having a plurality of electrode parts which are arranged on the insulating layer to be spaced from each other and which have a thickness larger than the first metal layer;   wherein the insulating layer has a plurality of via holes which connect the first metal layer and the plurality of electrode parts;   the wiring structure further comprising:   a plurality of through wiring lines which are located within the plurality of via holes and which electrically connect the plurality of electrode parts to the first metal layer.   
     
     
         2 . The wiring structure of a semiconductor device according to  claim 1 , wherein the plurality of electrode parts are arranged in a plurality of rows and in a plurality of columns. 
     
     
         3 . The wiring structure of a semiconductor device according to  claim 1 , wherein:
 each of the plurality of electrode parts has a planar shape of a quadrangle, and   the plurality of via holes are located in the vicinity of angular corners of the plurality of electrode parts respectively.   
     
     
         4 . The wiring structure of a semiconductor device according to  claim 1 , wherein:
 the first metal layer is made of a single wiring structural member, and   the wiring structural member is located to be opposed to the plurality of electrode parts with the insulating layer disposed therebetween.   
     
     
         5 . The wiring structure of a semiconductor device according to  claim 1 , wherein:
 the first metal layer is made of a plurality of wiring structural members, and   the plurality of wiring structural members are located to be opposed to the plurality of electrode parts with the insulating layer disposed therebetween.   
     
     
         6 . The wiring structure of a semiconductor device according to  claim 5 , wherein when the plurality of electrode parts are arranged in M rows and in N columns, each of M and N being an integer not smaller than two, the plurality of wiring structural members are arranged in rows in number not larger than (M−1) and in columns in number not larger than (N−1). 
     
     
         7 . The wiring structure of a semiconductor device according to  claim 1 , wherein the first metal layer, the through wiring lines, and the second metal layer are made of an identical conductive material. 
     
     
         8 . The wiring structure of a semiconductor device according to  claim 1 , wherein the base member is a semiconductor substrate. 
     
     
         9 . The wiring structure of a semiconductor device according to  claim 1 , wherein the base member is another layer formed on a semiconductor substrate. 
     
     
         10 . The wiring structure of a semiconductor device according to  claim 1 , wherein the second metal layer is a pad electrode to which a wiring line is to be bonded. 
     
     
         11 . A method of manufacturing a wiring structure of a semiconductor device, comprising:
 forming a first insulating layer on a base member;   forming a first metal layer on the first insulating layer;   forming a second insulating layer covering the first metal layer;   forming a plurality of via holes in the second insulating layer;   forming a plurality of through wiring lines which are provided within the plurality of via holes to be electrically connected to the first metal layer; and   forming a plurality of electrode parts which are arranged on the second insulating layer to be spaced from each other and are electrically connected to any of the plurality of through wiring lines, the plurality of electrode parts constituting the second metal layer and having a thickness larger than the first metal layer.   
     
     
         12 . The method of manufacturing a wiring structure of a semiconductor device according to  claim 11 , wherein the plurality of electrode parts are arranged in a plurality of rows and in a plurality of columns. 
     
     
         13 . The method of manufacturing a wiring structure of a semiconductor device according to  claim 11 , wherein each of the plurality of electrode parts has a planar shape of a quadrangle, and the plurality of via holes are arranged in the vicinity of angular corners of the plurality of electrode parts respectively. 
     
     
         14 . The method of manufacturing a wiring structure of a semiconductor device according to  claim 11 , wherein:
 the first metal layer is made of a single wiring structural member, and   the wiring structural member is arranged to be opposed to the plurality of electrode parts with the insulating layer disposed therebetween.   
     
     
         15 . The method of manufacturing a wiring structure of a semiconductor device according to  claim 11 , wherein:
 the first metal layer is made of a plurality of wiring structural members, and   the plurality of wiring structural members are arranged to be opposed to the plurality of electrode parts with the insulating layer disposed therebetween.   
     
     
         16 . The method of manufacturing a wiring structure of a semiconductor device according to  claim 15 , wherein when the plurality of electrode parts are arranged in M rows and in N columns, each of M and N being an integer not smaller in number than two, the plurality of wiring structural members are arranged in rows not larger in number than (M−1) and in columns not larger in number than (N−1). 
     
     
         17 . The method of manufacturing a wiring structure of a semiconductor device according to  claim 11 , wherein the first metal layer, the through wiring lines, and the second metal layer are made of an identical conductive material.