Stacked semiconductor chips packaging

Abstract

Various methods and apparatus for joining stacked substrates to a circuit board are disclosed. In one aspect, a method of manufacturing is provided that includes coupling plural substrates to form a stack. At least one of the plural substrates is a semiconductor chip. Plural conductive vias are formed in a first of the plural substrates. Each of the plural conductive vias includes a first end positioned in the first substrate and a second end projecting out of the first substrate.

1 . A method of manufacturing, comprising:
 coupling plural substrates to form a stack, wherein at least one of the plural substrates is a semiconductor chip; and   forming plural conductive vias in a first of the plural substrates, each of the plural conductive vias including a first end positioned in the first substrate and a second end projecting out of the first substrate.   
     
     
         2 . The method of  claim 1 , wherein a second of the plural substrates comprises a semiconductor chip. 
     
     
         3 . The method of  claim 1 , wherein a second of the plural substrates comprises an interposer. 
     
     
         4 . The method of  claim 1 , wherein the forming of the plural conductive vias comprises forming plural openings in the first substrate and forming at least the first ends of the plural conductors in the openings by plating. 
     
     
         5 . The method of  claim 1 , comprising positioning the second ends of the plural conductive vias proximate solder structures of a circuit board and reflowing the solder structures to wet the second ends. 
     
     
         6 . The method of  claim 5 , wherein the circuit board comprises a principal surface and the solder structures project beyond the principal surface. 
     
     
         7 . A method of manufacturing, comprising:
 providing a circuit board that includes an outermost surface and plural conductor pads;   forming a solder structure on each of the plural conductor pads, each of the solder structures including a portion projecting beyond the outermost surface; and   coupling the solder structures to corresponding conductive vias of a stack of substrates, wherein at least one of the substrates is a semiconductor chip.   
     
     
         8 . The method of  claim 7 , wherein the forming the solder structures comprises applying a mask to the circuit board, forming plural openings in the mask leading to the plural conductor pads, and forming the solder structures in the plural openings that project beyond an outermost surface of the mask. 
     
     
         9 . The method of  claim 7 , wherein the solder structures comprises pillars. 
     
     
         10 . The method of  claim 7 , wherein the solder structures comprises balls. 
     
     
         11 . An apparatus, comprising:
 a stack including plural substrates, wherein at least one of the plural substrates is a semiconductor chip; and   plural conductive vias coupled to a principal surface of a first of the plural substrates, each of the plural conductive vias including a first end positioned in the first substrate and a second end projecting away from the principal surface of the first substrate.   
     
     
         12 . The apparatus of  claim 11 , wherein a second of the plural substrates comprises an interposer. 
     
     
         13 . The apparatus of  claim 11 , comprising a circuit board including plural solder structures coupled to the second ends of the plural conductive vias. 
     
     
         14 . The apparatus of  claim 13 , wherein the circuit board comprises a principal surface and the solder structures project beyond the principal surface. 
     
     
         15 . The apparatus of  claim 14 , wherein the solder structures comprise solder pillars. 
     
     
         16 . The apparatus of  claim 14 , wherein the solder structures comprise solder balls. 
     
     
         17 . A semiconductor device comprising:
 a semiconductor chip comprising plural conductive vias coupled to a surface of the semiconductor chip, each of the plural conductive vias including a first end positioned in the semiconductor chip and a second end projecting away from the surface of the semiconductor chip, the plural conductive vias arranged to align in a stack configuration with a substrate.   
     
     
         18 . The semiconductor device of  claim 17  wherein the substrate comprises an interposer comprised of plural conductive vias aligned to stack with corresponding plural conductive vias in the semiconductor chip when in a stacked configuration.