Semiconductor device

Abstract

According to one embodiment, a semiconductor device includes N fins made of a semiconductor material aligned in parallel with each other; a first gate electrode formed on both side surfaces of each of the N fins to cross the fins; and a second gate electrode formed in parallel with the first gate electrode on both side surfaces of the N fins to cross the fins, and having a larger gate length than a gate length of the first gate electrode, wherein number of fins formed with contacts of source/drain layers of first field-effect transistors having the first gate electrode is larger than number of fins formed with contacts of source/drain layers of second field-effect transistors having the second gate electrode.

1 . A semiconductor device comprising:
 N (N is an integer equal to or larger than 2) fins made of a semiconductor material aligned in parallel with each other;   a first gate electrode formed on both side surfaces of each of the N fins to cross the fins; and   a second gate electrode formed in parallel with the first gate electrode on both side surfaces of the N fins to cross the fins, and having a larger gate length than a gate length of the first gate electrode, wherein   number of fins formed with contacts of source/drain layers of first field-effect transistors having the first gate electrode is larger than number of fins formed with contacts of source/drain layers of second field-effect transistors having the second gate electrode.   
     
     
         2 . The semiconductor device according to  claim 1 , further comprising at least one dummy fin aligned in parallel at outside of the N fins. 
     
     
         3 . The semiconductor device according to  claim 1 , wherein widths of the fins are equal to each other, and intervals between the fins are also equal to each other. 
     
     
         4 . The semiconductor device according to  claim 1 , wherein the contacts of the source/drain layers of the first field-effect transistors are aligned in each of the fins to be symmetrical with each other in the top view plain, and the contacts of the source/drain layers of the second field-effect transistors are aligned in each of the fins to be symmetrical with each other in the top view plain. 
     
     
         5 . The semiconductor device according to  claim 1 , wherein the fins are not doped with impurity. 
     
     
         6 . The semiconductor device according to  claim 1 , wherein a part of the gate electrode is configured by metal compounds. 
     
     
         7 . The semiconductor device according to  claim 1 , wherein if G represents drain conductance of the second field-effect transistors, g m  represents mutual conductance of the first field-effect transistors, r ds  represents a drain resistance, and R represents a parasitic resistance at a drain side, a relationship of G×R<g m ×r ds  is satisfied.