Structure with isotropic silicon recess profile in nanoscale dimensions

Abstract

A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.

1 . A semiconductor structure comprising:
 a gate structure located on a semiconductor material layer comprising a first semiconductor material, said gate structure including a gate dielectric, a gate conductor, and a gate spacer;   a semiconductor material portion embedded in said semiconductor material layer, said semiconductor material portion comprising a second semiconductor material that is different from said first semiconductor material; and   a non-planar interface region between said first semiconductor material and said second semiconductor material, wherein said non-planar interface region includes a first horizontal interface portion at a first depth from said gate dielectric, a second horizontal interface portion at a second depth from said gate dielectric, and a non-horizontal interface portion adjoined to said first horizontal interface portion and said second horizontal interface portion and underlying said gate spacer.   
     
     
         2 . The semiconductor structure of  claim 1 , further comprising a vertical interface between said first semiconductor material and said second semiconductor material, wherein said vertical interface underlies said gate spacer. 
     
     
         3 . The semiconductor structure of  claim 1 , further comprising a vertical interface between said first semiconductor material and said second semiconductor material, wherein said vertical interface underlies said gate dielectric. 
     
     
         4 . The semiconductor structure of  claim 1 , wherein said first and second semiconductor materials are single crystalline semiconductor materials that are epitaxially aligned to each other, and wherein said second semiconductor material is selected from a single crystalline silicon-germanium alloy, a single crystalline silicon-carbon alloy, and a single crystalline silicon-germanium-carbon alloy. 
     
     
         5 . The semiconductor structure of  claim 1 , wherein said semiconductor material portion applies stress to a portion of said semiconductor material layer. 
     
     
         6 . A method of forming a semiconductor structure comprising:
 forming a trench in a semiconductor material layer;   forming a contiguous semiconductor oxide liner on sidewalls and a bottom surface of said trench;   exposing sidewall surfaces of said trench by removing vertical portions of said contiguous semiconductor oxide liner while a remaining horizontal semiconductor oxide portion of said contiguous semiconductor oxide liner overlies a portion of said semiconductor material layer located underneath said trench, wherein said remaining horizontal semiconductor oxide portion includes a top surface that contiguously extends from one of said sidewall surfaces to another of said sidewall surfaces after said sidewall surfaces are exposed; and   laterally etching said sidewall surfaces of said trench while said remaining horizontal semiconductor oxide portion covers said portion of said semiconductor material layer located underneath said trench and a portion of said remaining horizontal semiconductor oxide portion is exposed within said trench.   
     
     
         7 . The method of  claim 6 , wherein said contiguous oxide liner is formed by converting said semiconductor material in said semiconductor material layer into a semiconductor oxide material. 
     
     
         8 . The method of  claim 7 , wherein a semiconductor material of said semiconductor material layer located at said bottom surface of said trench has a crystallographic orientation that provides a greater oxidation rate than crystallographic orientations of said sidewalls or said bottom surface is formed by exposing said trench to an oxygen-containing plasma having ion energies greater than a plasma potential. 
     
     
         9 . The method of  claim 8 , wherein said semiconductor material layer is a single crystalline silicon layer, a crystallographic orientation of said bottom surface and a crystallographic orientation of said sidewall surfaces have a combination of a <111> orientation and a <110> orientation, respectively, or a combination of a <110> orientation and a <100> orientation, respectively. 
     
     
         10 . The method of  claim 6 , wherein said semiconductor material layer has a first semiconductor material, and said method further comprises filling said trench with a second semiconductor material that is different from said first semiconductor material, wherein said second semiconductor material generates mechanical stress in a portion of said semiconductor material layer around said second semiconductor material. 
     
     
         11 . The method of  claim 10 , wherein said second semiconductor material is selected from a single crystalline silicon-germanium alloy, a single crystalline silicon-carbon alloy, and a single crystalline silicon-germanium-carbon alloy. 
     
     
         12 . The method of  claim 6 , further comprising forming a first gate structure and a second gate structure, wherein each of said first and second gate structure includes a gate dielectric, a gate conductor, and a gate spacer, and said sidewalls of said trench contacts outer peripheries of said gate spacers upon formation of said sidewalls. 
     
     
         13 . The method of  claim 6 , wherein said sidewall surfaces of said trench are laterally etched by a plasma etch. 
     
     
         14 . A method of forming a semiconductor structure comprising:
 forming a trench in a semiconductor material layer; and   forming an adsorbed fluorine layer on vertical surfaces of said trench, while horizontal surfaces of said trench do not have adsorbed fluorine thereupon.   
     
     
         15 . The method of  claim 14 , further comprising subjecting said adsorbed fluorine layer and said vertical surfaces of said trench to a temperature at which said adsorbed fluorine layer etches a semiconductor material on said vertical surfaces by reacting with said semiconductor material. 
     
     
         16 . The method of  claim 15 , wherein said adsorbed fluorine layer is formed on vertical surfaces of said trench at a cryogenic temperature below −40 degrees Celsius. 
     
     
         17 . The method of  claim 14 , wherein said adsorbed fluorine layer is formed as a contiguous adsorbed fluorine layer that extends across all exposed surfaces of said semiconductor structure. 
     
     
         18 . The method of  claim 17 , further comprising sputtering said contiguous adsorbed fluorine layer with ions, whereby horizontal portions of said contiguous adsorbed fluorine layer are removed and vertical portions of said contiguous adsorbed fluorine layer remain to constitute said adsorbed fluorine layer. 
     
     
         19 . The method of  claim 14 , wherein said adsorbed fluorine layer is a monolayer of fluorine atoms that are atomically bonded to an underlying semiconductor material in said semiconductor material layer. 
     
     
         20 . The method of  claim 14 , wherein said adsorbed fluorine layer is formed by exposing said trench to a fluorine-containing gas selected from F 2 , CClF 3 , SF 6 , XeF 2 , CF 4 , CHF 3 , CH 2 F 2 , CH 3 F, C 4 F 6 , C 5 F 8 , C 4 F 8  and a combination thereof at a cryogenic temperature below −40 degrees Celsius.