Graphics controller integrated circuit without memory interface

Abstract

A CMOS integrated circuit that comprises a graphics controller system that consists of a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for generating video images on a LCD or CRT display unit, and a video stream interface for receiving video signals. Since the video memory is integrated on the same integrated circuit as the graphics controller, no package pins are required for the memory interface. The pins thus saved are used to provide access to an on-chip PCMCIA host adapter. The internal memory interface is 128 bits wide. Simultaneous performance improvement and power dissipation reduction is achieved because of the wide memory interface and the elimination of the large parasitic capacitances associated with a package pin connection.

1 . A complementary MOS integrated circuit, comprising:
 circuitry for processing data associated with graphics information, the graphics information for display by an electronic system in which said complementary MOS integrated circuit resides, said circuitry including at least 30K logic gates, each such logic gate having at least two transistors;   a memory for storing and retrieving at least a portion of data associated with said graphics information, said memory having a capacity of at least 2 megabits; and   a data interface between said circuitry and said memory, said data interface being at least 128 bits wide;   whereby integration of said circuitry, said memory and said data interface in said complementary MOS integrated circuit results in a lower number of integrated circuit packages, and lower power dissipation, in said electronic system in which said complementary MOS integrated circuit resides.   
     
     
         2 . The complementary MOS integrated circuit of  claim 1 , wherein said memory comprises DRAM. 
     
     
         3 . A complementary MOS integrated circuit, comprising:
 circuitry for processing, controlling or manipulating video data, the video data for display by an electronic system in which said complementary MOS integrated circuit resides, said circuitry including at least 30K logic gates, each such logic gate having at least two transistors;   a memory for storing and retrieving at least a portion of said video data, said memory having a capacity of at least 2 megabits; and   a data interface between said circuitry and said memory, said data interface being at least 128 bits wide;   whereby integration of said circuitry, said memory and said data interface in said complementary MOS integrated circuit results in a lower number of integrated circuit packages, and lower power dissipation, in said electronic system in which said complementary MOS integrated circuit resides.   
     
     
         4 . The complementary MOS integrated circuit of  claim 3 , wherein said memory comprises DRAM. 
     
     
         5 . A complementary MOS integrated circuit, comprising:
 circuitry for processing data associated with graphics information, the graphics information for display by an electronic system in which said complementary MOS integrated circuit resides, said circuitry including at least 30K logic gates, each such logic gate;   a memory for storing and retrieving at least a portion of data associated with said graphics information, said memory having a capacity of at least 2 megabits; and   a data interface between said circuitry and said memory, said data interface being at least 128 bits wide;   whereby integration of said circuitry, said memory and said data interface in said complementary MOS integrated circuit results in a lower number of integrated circuit packages, and lower power dissipation, in said electronic system in which said complementary MOS integrated circuit resides.   
     
     
         6 . A complementary MOS integrated circuit, comprising:
 circuitry for processing, controlling or manipulating video data, the video data for display by an electronic system in which said complementary MOS integrated circuit resides, said circuitry including at least 30K logic gates, each such logic gate;   a memory for storing and retrieving at least a portion of said video data, said memory having a capacity of at least 2 megabits; and   a data interface between said circuitry and said memory, said data interface being at least 128 bits wide;   whereby integration of said circuitry, said memory and said data interface in said complementary MOS integrated circuit results in a lower number of integrated circuit packages, and lower power dissipation, in said electronic system in which said complementary MOS integrated circuit resides.   
     
     
         7 . The complementary MOS integrated circuit of  claim 6 , wherein said memory comprises DRAM.