Intruction folding mechanism, method for performing the same and pixel processing system employing the same
Abstract
Methods, systems, and apparatuses, including computer programs encoded on computer-readable medium, including an instruction scheduler for scanning first and second instructions that are operable to output data to different components in a register. A rule checker determines if the scanned first and second instructions are data independent. An instruction combiner, in response to a determination that the scanned first and second instructions are data independent, forms a combination of the scanned first and second instructions. A processing unit that includes a single decoder, receives the combination, decodes the combination using the single decoder, and executes the combination.
Claims
exact text as granted — not AI-modified1 . A system comprising:
an instruction scheduler configured to scan first and second instructions, wherein the first and second instructions are operable to output data to different components in a register; a rule checker configured to determine if the scanned first and second instructions are data independent; an instruction combiner configured, in response to a determination that the scanned first and second instructions are data independent, to form a combination of the scanned first and second instructions; and a processing unit comprising a single decoder, the processing unit operable to receive the combination, decode the combination using the single decoder, and execute the combination.
2 . The system of claim 1 , wherein the combination is a reduced instruction.
3 . The system of claim 1 , wherein the combination is a new instruction.
4 . The system of claim 1 , wherein the combination is part of a program.
5 . The system of claim 1 , wherein the combination is operable to output data to the register.
6 . The system of claim 1 , wherein the scanned first and second instructions have an identical target register.
7 . The system of claim 1 , wherein the scanned first and second instructions are adjacent in a program.
8 . The system of claim 1 , wherein the processing unit is operable to perform an operation of a plurality of register components of the combination.
9 . The system of claim 1 , wherein the scanned second instruction has a source register different than a target register of the first scanned instruction.
10 . A system comprising:
an instruction scheduler configured to scan first and second instructions each having one or more registers; a rule checker configured to determine if the scanned first and second instructions are data independent by comparing the one or more registers of the scanned first instruction with the one or more registers of the scanned second instruction; an instruction combiner configured, in response to a determination that the scanned first and second instructions are data independent, to form a combination of the scanned first and second instructions; and a processing unit comprising a single decoder, the processing unit operable to receive the combination, decode the combination using the single decoder, and execute the combination.
11 . A processing system comprising:
a checker operable to check for data independency between first and second instructions by comparing one or more target registers of said first instruction with one or more source registers of said second instruction; an instruction combiner operable to form a combination of said first and second instructions responsive to a determination by said checker that the first and second instructions are data independent; and a single decoder operable to decode the combination of said first and second instructions.
12 . The system of claim 11 , wherein the combination is a reduced instruction.
13 . The system of claim 11 , wherein the combination is a new instruction.Join the waitlist — get patent alerts
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