Insulating layers on different semiconductor materials

Abstract

A semiconductor structure is provided that includes a substrate having disposed thereon a silicon layer and a silicon germanium layer. An insulator is disposed between the silicon layer and the silicon germanium layer. An optional silicon nitride film is disposed conformally on the silicon layer and the silicon germanium layer, and a SiO 2 layer disposed on the optional silicon nitride film or on the silicon layer and the silicon germanium layer, when the optional silicon nitride film is not present.

1 . A semiconductor structure, comprising:
 a substrate having disposed thereon a silicon layer and a silicon germanium layer;   an insulator disposed between the silicon layer and the silicon germanium layer;   a silicon nitride film disposed conformally on the silicon layer and the silicon germanium layer; and   a SiO 2  layer disposed on the silicon nitride film.   
     
     
         2 . The structure as claimed in  claim 1  wherein the silicon germanium layer has a Ge concentration of approximately 20%. 
     
     
         3 . The structure of  claim 1  wherein said insulator has an upper most surface that is coplanar within an uppermost surface of each of said silicon layer and said silicon germanium layer. 
     
     
         4 . The structure of  claim 1  wherein said insulator has one vertical sidewall in direct physical contact with a vertical sidewall of said silicon layer and another vertical sidewall in direct physical contact with a vertical sidewall of said silicon germanium layer. 
     
     
         5 . The structure of  claim 1  wherein said substrate comprises bulk silicon. 
     
     
         6 . The structure of  claim 1  wherein said silicon germanium layer is present at a p-FET region of the substrate, and the silicon layer is present at an n-FET region of said substrate. 
     
     
         7 . The structure of  claim 1  wherein said silicon germanium layer consists essentially of silicon and germanium, and said silicon layer consists essentially of silicon. 
     
     
         8 . The structure of  claim 1  wherein said SiO 2 layer has a thickness that is greater than a thickness of said silicon nitride film. 
     
     
         9 . The structure of  claim 1  wherein an n-FET gate stack is present on a portion of said SiO 2  layer that is located atop said silicon layer, and wherein a p-FET gate stack is present atop another portion of said SiO 2 layer that is located atop said silicon germanium layer, said n-FET gate stack is comprised of different materials that said p-FET gate stack. 
     
     
         10 . The structure of  claim 9  wherein said n-FET gate stack comprises, from bottom to top, HfO 2  or HfSiO x , La 2 O 3 , TiN and polysilicon. 
     
     
         11 . The structure of  claim 10  wherein said n-FET gate stack comprises, from bottom to top, HfO 2  or HfSiO x , TiN and polysilicon. 
     
     
         12 . A semiconductor structure, comprising:
 a substrate having disposed thereon a silicon layer and a silicon germanium layer;   an insulator disposed between the silicon layer and the silicon germanium layer; and   a SiO 2 layer disposed on the silicon layer and the silicon germanium layer.   
     
     
         13 . The structure as claimed in  claim 12  wherein the silicon germanium layer has a Ge concentration of approximately 20%. 
     
     
         14 . The structure of  claim 12  wherein said insulator has an upper most surface that is coplanar within an uppermost surface of each of said silicon layer and said silicon germanium layer. 
     
     
         15 . The structure of  claim 12  wherein said insulator has one vertical sidewall in direct physical contact with a vertical sidewall of said silicon layer and another vertical sidewall in direct physical contact with a vertical sidewall of said silicon germanium layer. 
     
     
         16 . The structure of  claim 12  wherein said substrate comprises bulk silicon. 
     
     
         17 . The structure of  claim 12  wherein said silicon germanium layer is present at a p-FET region of the substrate, and the silicon layer is present at an n-FET region of said substrate. 
     
     
         18 . The structure of  claim 12  wherein said silicon germanium layer consists essentially of silicon and germanium, and said silicon layer consists essentially of silicon. 
     
     
         19 . The structure of  claim 12  wherein an n-FET gate stack is present on a portion of said SiO 2  layer that is located atop said silicon layer, and wherein a p-FET gate stack is present atop another portion of said SiO 2 layer that is located atop said silicon germanium layer, said n-FET gate stack is comprised of different materials that said p-FET gate stack. 
     
     
         20 . The structure of  claim 9  wherein said n-FET gate stack comprises, from bottom to top, HfO 2  or HfSiO x , La 2 O 3 , TiN and polysilicon, and said n-FET gate stack comprises, from bottom to top, HfO 2  or HfSiO x , TiN and polysilicon.