Test access port with address and command capability

Abstract

The disclosure provides a novel method and apparatus for inputting addresses to devices to select the device TAP for access. Further, the disclosure provides a novel method and apparatus for inputting addresses for selecting device TAPs and for inputting commands for commanding circuitry within the device. The inputting of addresses or the inputting of addresses and commands is initiated by a control bit input on TDI that is recognized during the Run Test/Idle, Pause-DR or Pause-IR TAP states.

1 . An integrated circuit comprising:
 A. a test data in lead;   B. a test clock in lead;   C. a test mode select in lead;   D. a test data out lead;   E. an instruction register coupled with the test data in lead and the test data out lead, the instruction register having a control input and a control output;   F. a data register coupled with the test data in lead and the test data out lead, the data register having a control input coupled to the control output of the instruction register; and   G. addressable port circuitry including state machine circuitry coupled with the test mode select in lead and the test clock in lead, the addressable port circuitry having a control output coupled with the instruction register and the data register, the addressable port circuitry including addressing circuitry that is coupled to the test data in lead, the test clock in lead, and the test mode select in lead, the addressing circuitry including address circuitry having an enable output, and the addressable port circuitry including gating circuitry having an input connected to the enable output, and input connected with the test mode select in lead and an output connected with the state machine circuitry.   
     
     
         2 . The integrated circuit of  claim 1  in which the state machine circuitry cycles through states of Test Logic Reset, Run Test/Idle, Select-DR, Capture-DR, Shift-DR, Update-DR, Select-IR, Capture-IR, Shift-IR and Update-IR. 
     
     
         3 . The integrated circuit of  claim 1  including:
 A. a second instruction register coupled with the test data in lead and the test data out lead, the second instruction register having a control input and a control output; 
 B. a second data register coupled with the test data in lead and the test data out lead, the second data register having a control input coupled to the control output of the second instruction register; and 
 C. second addressable port circuitry including second state machine circuitry coupled with the test mode select in lead and the test clock in lead, the second addressable port circuitry having a control output coupled with the second instruction register and the second data register, the second addressable port circuitry including second addressing circuitry coupled to the test data in lead, the test clock in lead, and the test mode select in lead, and second gating circuitry coupled with the second addressing circuitry and selectively connecting the test mode select in lead with the second state machine circuitry. 
 
     
     
         4 . The integrated circuit of  claim 3  in which the second state machine circuitry cycles through states of Test Logic Reset, Run Test/Idle, Select-DR, Capture-DR, Shift-DR, Update-DR, Select-IR, Capture-IR, Shift-IR and Update-IR.