US2012182273A1PendingUtilityA1

Data processing device and semiconductor device

Assignee: NINOMIYA SHINYUPriority: Jan 17, 2011Filed: Jan 13, 2012Published: Jul 19, 2012
Est. expiryJan 17, 2031(~4.5 yrs left)· nominal 20-yr term from priority
G06F 3/1431G09G 2350/00G09G 5/006G09G 2360/04G09G 2370/10
43
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Claims

Abstract

Data transfer is enabled according to the reception capability of each of peripherals when a plurality of peripherals is connected to a host device via common lanes. A data processing device 1 includes a host device 10 provided with an interface, a first device 12 connected to the interface via a plurality of data lanes, and a second device 13 connected to the interface via some of the data lanes. The interface adds dummy data to actual data and then assigns and transmits the resultant data to the data lanes. When the actual data is taken in one of the first device and the second device, the interface causes the other one to recognize that the actual data is meaningless. Therefore, data can be transferred to the first device 12 and the second device 13 in accordance with reception capabilities.

Claims

exact text as granted — not AI-modified
1 . A data processing device, comprising:
 a host device provided with an interface which can be connected to a plurality of data lanes in differential serial communication;   a first device connected to the interface via the data lanes; and   a second device connected to the interface via some of the above data lanes, wherein   the interface adds dummy data to actual data and then assigns and transmits the resultant data to the data lanes, and   when the actual data is taken in one of the first device and the second device, the interface causes the other one to recognize that the actual data is meaningless.   
     
     
         2 . The data processing device according to  claim 1 ,
 wherein transmission data to the first device is assigned sequentially to the data lanes from the data lane having the smallest lane number and is formed to finish at the data lane having the largest lane number.   
     
     
         3 . The data processing device according to  claim 2 ,
 wherein actual data transmission to the second device starts from the data lane having the smallest lane number.   
     
     
         4 . The data processing device according to  claim 3 ,
 wherein the interface performs data output on the first device in order of the dummy data, the actual data, and the dummy data.   
     
     
         5 . The data processing device according to  claim 4 ,
 wherein the interface includes a register which can set the number of data lanes corresponding to the second device.   
     
     
         6 . The data processing device according to  claim 5 ,
 wherein the first device is a first liquid crystal display, and the second device is a second liquid crystal display having a resolution lower than the first liquid crystal display.   
     
     
         7 . The data processing device according to  claim 6 ,
 wherein the interface supplies image data sets for display to both of the first liquid crystal display and the second liquid crystal display in a time-division method by outputting data in the same method.   
     
     
         8 . A semiconductor device provided with an interface which can be connected to a plurality of data lanes in differential serial communication, the interface comprising:
 a transmission circuit for transmitting data via the data lanes; and   a transmission control circuit which can control operation of the transmission circuit, wherein   the transmission circuit adds dummy data to actual data and then assigns and transmits the resultant data to the data lanes, in a state in which the transmission circuit is connected to a first device via the data lanes and also connected to a second device via some data lanes among the data lanes, and,   when the actual data is taken in one of the first device and the second device, the transmission circuit causes the other one to recognize that the actual data is meaningless.   
     
     
         9 . The semiconductor device according to  claim 8 , wherein
 the interface includes a register which can set the number of data lanes corresponding to the second device, and   the transmission control circuit controls operation of the transmission circuit in accordance with setting information of the register.

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