Semiconductor Device and Method of Forming Bond Wires and Stud Bumps in Recessed Region of Peripheral Area around the Device for Electrical Interconnection to Other Devices

Abstract

A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A recessed region with angled or vertical sidewall is formed in the peripheral area. A conductive layer is formed in the recessed region. A first stud bump is formed over a contact pad of the semiconductor die. A second stud bump is formed over the first conductive layer within the recessed region. A bond wire is formed between the first and second stud bumps. A third stud bump is formed over the bond wire and first stud bump. A dicing channel partially formed through the peripheral area. The semiconductor wafer undergoes backgrinding to the dicing channel to singulate the semiconductor wafer and separate the semiconductor die. The semiconductor die can be disposed in a semiconductor package with other components and electrically interconnected through the bond wire and stud bumps.

1 . A semiconductor device, comprising:
 a semiconductor wafer having a plurality of semiconductor die with a recessed peripheral region around the semiconductor die;   a first conductive layer formed within the recessed peripheral region;   a first bump formed over the semiconductor die;   a second bump formed over the first conductive layer;   a bond wire formed between the first bump and second bump;   a third bump formed over the bond wire and first bump; and   an encapsulant deposited over the semiconductor wafer.   
     
     
         2 . The semiconductor device of  claim 1 , further including an insulating layer formed over the semiconductor die. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the third bump is exposed from the encapsulant. 
     
     
         4 . The semiconductor device of  claim 1 , further including a notch formed in the encapsulant to expose the third bump. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the encapsulant includes an organic material. 
     
     
         6 . The semiconductor device of  claim 1 , further including a second conductive layer formed over the encapsulant and electrically connected to the third bump. 
     
     
         7 . A semiconductor device, comprising:
 a semiconductor die having a peripheral region around the semiconductor die;   a first conductive layer formed within the peripheral region;   a first bump formed over the semiconductor die;   a bond wire formed between the first conductive layer and first bump;   a second bump formed over the bond wire and first bump; and   an encapsulant deposited over the semiconductor die.   
     
     
         8 . The semiconductor device of  claim 7 , further including a third bump formed over the first conductive layer and electrically connected to the bond wire. 
     
     
         9 . The semiconductor device of  claim 7 , wherein the second bump is exposed from the encapsulant. 
     
     
         10 . The semiconductor device of  claim 7 , further including a notch formed in the encapsulant to expose the second bump. 
     
     
         11 . The semiconductor device of  claim 7 , further including a second conductive layer formed over the encapsulant and electrically connected to the second bump. 
     
     
         12 . The semiconductor device of  claim 7 , further including:
 a semiconductor package; and   a semiconductor component disposed in the semiconductor package, wherein the semiconductor die is disposed in the semiconductor package with the semiconductor component and electrically connected to the semiconductor component through the bond wire.   
     
     
         13 . The semiconductor device of  claim 7 , further including a plurality of stacked semiconductor die electrically connected through the bond wire. 
     
     
         14 . A semiconductor device, comprising:
 a semiconductor die having a peripheral region around the semiconductor die;   a first bump formed over the semiconductor die;   a second bump formed within the peripheral region;   an interconnect structure formed between the first bump and second bump; and   an encapsulant deposited over the semiconductor die.   
     
     
         15 . The semiconductor device of  claim 14 , further including a first conductive layer formed within the peripheral region prior to forming the second bump. 
     
     
         16 . The semiconductor device of  claim 14 , further including a third bump formed over the interconnect structure and first bump. 
     
     
         17 . The semiconductor device of  claim 16 , further including a second conductive layer formed over the encapsulant and electrically connected to the third bump. 
     
     
         18 . The semiconductor device of  claim 14 , further including a second conductive layer formed over the semiconductor die and electrically connected to the second bump. 
     
     
         19 . The semiconductor device of  claim 14 , wherein the interconnect structure include a bond wire. 
     
     
         20 . The semiconductor device of  claim 14 , further including a plurality of stacked semiconductor die electrically connected through the interconnect structure. 
     
     
         21 . A semiconductor device, comprising:
 a semiconductor die having a peripheral region around the semiconductor die;   a first bump formed over the semiconductor die;   a second bump formed within the peripheral region;   an interconnect structure formed between the first bump and second bump; and   a third bump formed over the interconnect structure and first bump.   
     
     
         22 . The semiconductor device of  claim 21 , further including an encapsulant deposited over the semiconductor die. 
     
     
         23 . The semiconductor device of  claim 22 , wherein the second bump and third bump are exposed from the encapsulant. 
     
     
         24 . The semiconductor device of  claim 22 , further including a second conductive layer formed over the encapsulant and electrically connected to the third bump. 
     
     
         25 . The semiconductor device of  claim 21 , wherein the interconnect structure includes a bond wire.