Core via for chip package and interconnect

Abstract

In integrated circuit packages, core vias are created to provide electrical connections between circuitry on one face of the core substrate material with circuitry on an opposing face of the core substrate material. Provided are methods for forming a via in a packaging substrate and packaging substrates having core vias formed in the core substrate material. Methods for forma a core via in a packaging substrate in which a first hole is created through the core substrate and filled with a low permittivity filler material. A second co-axially aligned hole is then created in the low permittivity filler material wherein the second hole is smaller in diameter than the first hole. The second hole is then filled with conducting material to provide a conducting via through the core substrate material.

1 . A method for forming a via in a packaging core substrate comprising,
 providing a substrate in which one or more vias are to be formed;   creating a first hole through the substrate;   filling the first hole in the substrate with a low-permittivity filler material wherein the first hole is not plated with a metal before the low-permittivity filler material is placed in the first hole;   creating a second hole within the first hole through the non-conducting filler material wherein the second hole is smaller in diameter than the first hole; and   filling the second hole with a conducting material.   
     
     
         2 . The method of  claim 1  wherein the first hole through the substrate has a diameter between 100 μm to 1000 μm. 
     
     
         3 . The method of  claim 1  wherein the second hole through the non-conducting filler material has a diameter between 50 μm and 200 μm. 
     
     
         4 . The method of  claim 1  wherein the substrate is comprised of a material selected from the group consisting of epoxy resin embedded with glass fiber and epoxy resin embedded with glass fiber cloth. 
     
     
         5 . The method of  claim 1  wherein the substrate in one dimension has a thickness of between 100 and 1200 μm, wherein the first core via hole has a length, and wherein the length of the first core via hole is defined by the thickness of the substrate. 
     
     
         6 . The method of  claim 1  wherein the substrate in one dimension has a thickness of between 250 and 1000 μm, wherein the first core via hole has a length, and wherein the length of the first core via hole is defined by the thickness of the substrate. 
     
     
         7 . The method of  claim 1  wherein the non-conducting filler material is an epoxy resin. 
     
     
         8 . The method of  claim 1  also including placing a cap of conducting material on the second hole that is filled with conducting material. 
     
     
         9 . The method of  claim 1  wherein the second co-axially aligned hole is created through a laser drilling process.