Method and apparatus for a hierarchical synchronization barrier in a multi-node system

Abstract

A hierarchical barrier synchronization of cores and nodes on a multiprocessor system, in one aspect, may include providing by each of a plurality of threads on a chip, input bit signal to a respective bit in a register, in response to reaching a barrier; determining whether all of the plurality of threads reached the barrier by electrically tying bits of the register together and “AND”ing the input bit signals; determining whether only on-chip synchronization is needed or whether inter-node synchronization is needed; in response to determining that all of the plurality of threads on the chip reached the barrier, notifying the plurality of threads on the chip, if it is determined that only on-chip synchronization is needed; and after all of the plurality of threads on the chip reached the barrier, communicating the synchronization signal to outside of the chip, if it is determined that inter-node synchronization is needed.

1 . A method for a hierarchical barrier synchronization of cores and nodes on a multiprocessor system, comprising:
 providing by each of a plurality of threads on a chip, input bit signal to a respective bit in a register, in response to reaching a barrier;   determining whether all of the plurality of threads reached the barrier by electrically tying bits of the register together and “AND”ing the input bit signals;   determining whether only on-chip synchronization is needed or whether inter-node synchronization is needed;   in response to determining that all of the plurality of processors on the chip reached the barrier, notifying the plurality of threads on the chip, if it is determined that only on-chip synchronization is needed; and   after all of the plurality of threads on the chip reached the barrier, communicating the synchronization signal to outside of the chip, if it is determined that inter-node synchronization is needed.   
     
     
         2 . The method of  claim 1 , wherein the plurality of cores on the chip are heterogeneous. 
     
     
         3 . The method of  claim 1 , wherein the notifying the plurality of threads includes generating an interrupt, waking up the threads, or setting a bit indicating that the barrier has been achieved, or combinations thereof. 
     
     
         4 . The method of  claim 1 , further including:
 in response to determining that the inter-node synchronization is needed, hierarchically integrating the synchronization signal into a system synchronization; and   propagating a global synchronization signal back to one or more lower levels of synchronization down to all threads participating in the barrier.   
     
     
         5 . The method of  claim 4 , wherein a plurality of chips participate in the system synchronization and the plurality of chips are heterogeneous. 
     
     
         6 . The method of  claim 1 , wherein said each of a plurality of threads on a chip is programmed to sleep after providing the input bit signal. 
     
     
         7 . The method of  claim 6 , wherein said notifying the plurality of threads on the chip wakes up said each of a plurality of threads on a chip. 
     
     
         8 . A computer readable storage medium storing a program of instructions executable by a machine to perform a method for a hierarchical barrier synchronization of cores and nodes on a multiprocessor system, comprising:
 providing by each of a plurality of threads on a chip, input bit signal to a respective bit in a register, in response to reaching a barrier;   determining whether all of the plurality of threads reached the barrier by electrically tying bits of the register together and “AND”ing the input bit signals;   determining whether only on-chip synchronization is needed or whether inter-node synchronization is needed;   in response to determining that all of the plurality of threads on the chip reached the barrier, notifying the plurality of threads on the chip, if it is determined that only on-chip synchronization is needed; and   after all of the plurality of threads on the chip reached the barrier, communicating the synchronization signal to outside of the chip, if it is determined that inter-node synchronization is needed.   
     
     
         9 . The computer readable storage medium of  claim 8 , wherein the plurality of threads on the chip are heterogeneous. 
     
     
         10 . The computer readable storage medium of  claim 8 , wherein the notifying the plurality of threads includes generating an interrupt, waking up one or more of the plurality of threads, or setting a bit indicating the barrier has been achieved, or combinations thereof. 
     
     
         11 . The computer readable storage medium of  claim 8 , further including:
 in response to determining that the inter-node synchronization is needed, hierarchically integrating the synchronization signal into a system synchronization; and   propagating a global synchronization signal back to one or more lower levels of synchronization down to all threads participating in the barrier.   
     
     
         12 . The computer readable storage medium of  claim 11 , wherein a plurality of thread chips participate in the system synchronization and the plurality of thread chips are heterogeneous. 
     
     
         13 . The computer readable storage medium of  claim 8 , wherein said each of a plurality of threads on a chip is programmed to sleep after providing the input bit signal. 
     
     
         14 . The computer readable storage medium of  claim 13 , wherein said notifying the plurality of threads on the chip wakes up said each of a plurality of threads on a chip. 
     
     
         15 . An apparatus for a hierarchical barrier synchronization of cores and nodes on a multiprocessor system, comprising:
 a plurality of cores arranged in an integrated circuit;   a register operable to store input bit signals received from each of said plurality of cores;   a control logic circuit operable to electrically tie and perform a Boolean “AND” function on said stored input bit signals to determine whether said plurality of cores all achieved barrier, the control logic circuit further operable to determine whether only on-chip synchronization is needed or whether inter-node synchronization is needed, and in response to determining that all of the plurality of cores on the integrated circuit reached the barrier, notifying the plurality of cores on the chip, if it is determined that only on-chip synchronization is needed, and after all of the plurality of cores on the integrated circuit reached the barrier, communicating the synchronization signal to outside of the integrated circuit, if it is determined that inter-node synchronization is needed.   
     
     
         16 . The apparatus of  claim 15 , wherein the plurality of cores on the integrated circuit are heterogeneous. 
     
     
         17 . The apparatus of  claim 15 , wherein the notifying the plurality of cores on the integrated circuit includes transmitting a synchronization signal to said each of a plurality of cores on the integrated circuit. 
     
     
         18 . The apparatus of  claim 15 , further including:
 in response to determining that the inter-node synchronization is needed, hierarchically integrating the synchronization signal into a system synchronization; and   propagating a global synchronization signal back to one or more lower levels of synchronization down to all cores participating in the barrier.   
     
     
         19 . The apparatus of  claim 18 , wherein a plurality of integrated circuits participates in the system synchronization and the plurality of integrated circuits are heterogeneous. 
     
     
         20 . The apparatus of  claim 15 , wherein said each of a plurality of cores in integrated circuit is programmed to sleep after providing the input bit signal. 
     
     
         21 . The apparatus of  claim 20 , wherein said notifying the plurality of cores in the integrated circuit wakes up said each of a plurality of cores. 
     
     
         22 . The apparatus of  claim 21 , further including instruction set architecture that includes an instruction to set barrier and an instruction to wakeup one or more cores. 
     
     
         23 . The apparatus of  claim 15 , wherein the register is further operable to store a mask bit corresponding to each of the plurality of cores, the mask bit for indicating whether the corresponding cores is participating in barrier synchronization.