Leadless semiconductor package and method of manufacture

Abstract

A leadless semiconductor package includes a package body on a leadframe that includes a die paddle and a plurality of bond pads, none of which extend as far as a lateral face of the body. During manufacture of the package, molding compound is deposited over a face of the leadframe on which the die paddle and bond pads are positioned. After the molding compound is cured, a back side of the leadframe is etched to isolate the die paddle and bond pads, back surfaces of which remain exposed at a back face of the body. During manufacture of the leadframe, a parent substrate is etched to define the die paddle and a plurality of bond pads on one side of the substrate and a plurality of cavities on the opposite face.

1 . A semiconductor package, comprising:
 a package body;   a die paddle of a first metal, with a layer of a second metal, different from the first metal, positioned on a front surface of the die paddle and a layer of a third metal, different from the first metal, positioned on a back surface of the die paddle, the die paddle positioned in the body so that the back surface of the die paddle is exposed at a back surface of the body;   a semiconductor die affixed to the front surface of the die paddle over the first layer and encapsulated within the body; and   a plurality of bond pads of the first metal, each having a layer of the second metal positioned on a respective front surface and a layer of the third metal positioned on a respective back surface, each being encapsulated within the body with a respective back surface exposed at the back surface of the body, and no portion exposed at a lateral face of the body.   
     
     
         2 . The package of  claim 1  wherein the die paddle and each of the plurality of bond pads are thinner than about 100 microns. 
     
     
         3 . The package of  claim 1  wherein the die paddle and each of the plurality of bond pads are thinner than about 50 microns. 
     
     
         4 . The package of  claim 1  wherein the die paddle and each of the plurality of bond pads are between about 10 microns and about 80 microns. 
     
     
         5 . The package of  claim 1 , comprising a contact ring of the first metal, lying in a common plane with the die paddle and positioned to encircle the die paddle, and having a back surface exposed at the back surface of the body. 
     
     
         6 . The package of  claim 1  wherein the second and third metals are a same metal. 
     
     
         7 . A leadframe for a semiconductor package, comprising:
 a substrate of a first metal, having first and second surfaces and extending laterally without substantial perforations over a first area;   a plurality of lands coupled to the substrate on the first surface entirely within the first area; and   a plurality of cavities formed in the second surface of the substrate without extending through the substrate, each in a position opposite a respective one of the plurality of lands.   
     
     
         8 . The leadframe of  claim 7  wherein each of the plurality of cavities has lateral dimensions that are less than corresponding lateral dimensions of the corresponding land opposite. 
     
     
         9 . The leadframe of  claim 7  wherein a depth of each of the plurality of cavities is approximately equal to a height of each of the plurality of lands above the first surface. 
     
     
         10 . The leadframe of  claim 7  wherein each of the plurality of lands has a face on which a layer of a second metal is deposited. 
     
     
         11 . The leadframe of  claim 7  wherein each of the plurality of cavities has an inner wall on which a layer of a second metal is deposited. 
     
     
         12 . The leadframe of  claim 7  wherein one of the plurality of lands is a die paddle, and others of the plurality of lands are bond pads. 
     
     
         13 . A method, comprising:
 etching a first depth into a first face of a substrate and forming thereby a plurality of lands of a leadframe, the first depth being less than an initial thickness of the substrate; and   etching a plurality of cavities a second depth into a second face of the substrate, each positioned opposite a respective one of the lands, the second depth being less than the initial thickness of the substrate.   
     
     
         14 . The method of  claim 13 , comprising plating a layer of metal over the first face of the substrate. 
     
     
         15 . The method of  claim 14 , comprising defining lateral dimensions of each of the plurality of lands by patterning the layer of metal. 
     
     
         16 . The method of  claim 13 , comprising plating a layer of metal on an inner surface of each of the plurality of cavities. 
     
     
         17 . The method of  claim 13 , comprising defining, among the lands of the leadframe, a die paddle and a plurality of bond pads. 
     
     
         18 . A method, comprising:
 affixing a semiconductor die to a first surface of a leadframe;   placing contact pads of the die in electrical contact with corresponding bond pads of the leadframe;   depositing a molding compound over the semiconductor die on the first surface of the leadframe;   curing the molding compound on the first surface of the leadframe; and   exposing portions of a surface of the cured molding compound by removing corresponding portions of the leadframe, while leaving portions of the leadframe embedded in the molding compound.   
     
     
         19 . The method of  claim 18  wherein the removing comprises etching a second surface of the leadframe, opposite the first surface. 
     
     
         20 . The method of  claim 18  wherein the leaving comprises selectively etching the second surface of the leadframe without etching portions of the second surface over which a metallic layer is deposited. 
     
     
         21 . The method of  claim 18  wherein the placing comprises placing contact pads of the die in electrical contact with bond pads that are positioned on the first surface of the leadframe substantially opposite corresponding portions of the second surface over which a metallic layer is deposited. 
     
     
         22 . The method of  claim 18  wherein the affixing comprises affixing the semiconductor die to a die paddle that is positioned on the first surface of the leadframe.